公开(公告)号：US20190334079A1

公开(公告)日：2019-10-31

申请号：US16463821

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Justin S. BROCKMAN ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.

公开(公告)号：US20190036010A1

公开(公告)日：2019-01-31

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian MAERTZ ,  Christopher J. WIEGAND ,  Daniel G. OEULLETTE ,  MD Tofizur RAHMAN ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Tahir GHANI ,  Brian S. DOYLE ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Kaan OGUZ

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US20190027679A1

公开(公告)日：2019-01-24

申请号：US16070415

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Christopher J. WIEGAND ,  MD Tofizur RAHMAN ,  Brian MAERTZ ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Tahir GHANI ,  Mark L. DOCZY

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.

公开(公告)号：US20170365677A1

公开(公告)日：2017-12-21

申请号：US15673219

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Uday SHAH ,  Brian S. DOYLE ,  Justin K. BRASK ,  Robert S. CHAU ,  Thomas A. LETSON

IPC: H01L29/423 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20170012117A1

公开(公告)日：2017-01-12

申请号：US15120496

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，由第一过渡金属二硫属元素（TMD）材料形成的第一阻挡层，由第二TMD材料形成的晶体管沟道和由第三TMD材料形成的第二阻挡层。 第一势垒可以设置在晶体管沟道和柔性衬底之间，晶体管沟道可以设置在第二栅极和第一势垒之间，晶体管沟道的带隙可能小于第一势垒的带隙，而小于 第二个屏障的带隙。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160043302A1

公开(公告)日：2016-02-11

申请号：US14887168

申请日：2015-10-19

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Charles C. KUO ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Uday SHAH

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

Abstract translation: 具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。 实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。 由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能 。