公开(公告)号：US10886218B2

公开(公告)日：2021-01-05

申请号：US16456647

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Chee Seng Leong ,  Lai Guan Tang ,  Han Wooi Lim ,  Hee Kong Phoon

IPC: H01L23/528 ,  H01L23/498 ,  H03K19/177 ,  H03K19/17704

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

公开(公告)号：US20200226313A1

公开(公告)日：2020-07-16

申请号：US16833122

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US10714163B2

公开(公告)日：2020-07-14

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

公开(公告)号：US10579552B1

公开(公告)日：2020-03-03

申请号：US15429018

申请日：2017-02-09

Applicant: Intel Corporation

Inventor： Chee Hak Teh

IPC: G06F13/16 ,  G06F13/364 ,  G06F13/42 ,  G06F5/06

Abstract: A communication interface includes one or more input/output circuitries, each input/output circuitry including a pointer generation block that controls write pointers of a respective input/output circuitry and read pointers of the respective input/output circuitry. Each input/output circuitry also includes input/output buffers communicatively coupled to the pointer generation block. Each input/output circuitry further includes a receive delay-locked loop that provides a clock signal to the plurality of input/output buffers. Each input/output circuitry also includes one or more transmit delay-locked loops that delay the clock signal.

公开(公告)号：US20190220566A1

公开(公告)日：2019-07-18

申请号：US16368696

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Chee Hak Teh

IPC: G06F17/50 ,  H01L25/18 ,  H01L23/00 ,  G06F13/20 ,  H04J3/02

CPC classification number: G06F17/5054 ,  G06F13/20 ,  G06F2217/66 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1436 ,  H04J3/02

Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.

公开(公告)号：US20190138680A1

公开(公告)日：2019-05-09

申请号：US16235933

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F17/50 ,  H03K19/177 ,  G06F15/78 ,  H04L12/43

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US10079211B1

公开(公告)日：2018-09-18

申请号：US15719303

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh

IPC: H01L23/52 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5382 ,  H01L21/563 ,  H01L23/5381 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06568

Abstract: An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the integrated circuit device. The integrated circuit device(s) also include external connection ports to transmit data to or receive data from outside the integrated circuit device, such as between integrated circuit devices. The integrated circuit device also includes remapping circuitry that remaps from a first connection between a first internal connection port of the internal connection ports and a first external connection port of the external connection ports to a second connection between a second internal connection port of the internal connection ports and a second external connection port of the external connection ports.

公开(公告)号：US12153866B2

公开(公告)日：2024-11-26

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  G06F15/78 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/43

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11995028B2

公开(公告)日：2024-05-28

申请号：US18089237

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F13/1631 ,  G06F13/1673 ,  G06F13/4004

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US11979152B2

公开(公告)日：2024-05-07

申请号：US17181973

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Chee Hak Teh

IPC: H03K19/17 ,  G06F11/10 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419 ,  G11C29/52 ,  H03K19/17736 ,  H03K19/1776 ,  G11C8/06 ,  G11C29/04

CPC classification number: H03K19/17744 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1015 ,  G11C11/418 ,  G11C11/419 ,  G11C29/52 ,  H03K19/1776 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/06 ,  G11C2029/0411

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.