Patent search ap:("INTEL CORPORATION") AND inv:"Darren S. Jue" Page 4

31.

发明申请
HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
Title translation: 高性能互连物理层

公开(公告)号：US20150205741A1

公开(公告)日：2015-07-23

申请号：US14672107

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer

IPC: G06F13/40 , G06N99/00

CPC classification number: G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151

Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.

Abstract translation: 生成一组训练序列，每个训练序列包括相应的训练序列头部，训练序列头部将在训练序列集合上进行DC平衡。训练序列的集合可以与电子有序集合组合以形成用于诸如链路适配，链路状态转换，字节锁定，偏斜校正和其他任务之类的任务的超序列。

32.

发明申请
HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
Title translation: 高性能互连物理层

公开(公告)号：US20150067208A1

公开(公告)日：2015-03-05

申请号：US14538937

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra DAS Sharma , Jeffrey C, Swanson

IPC: G06F13/42 , G06N99/00

CPC classification number: G06F13/4291 , G06F1/24 , G06F1/3287 , G06F13/1678 , G06F13/42 , G06F13/4282 , G06N99/005

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract translation: 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

33.

发明申请
HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
Title translation: 高性能互连物理层

公开(公告)号：US20150067207A1

公开(公告)日：2015-03-05

申请号：US14538897

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer , Darren S. Jue , Rahul Shah , Arvind Kumar

IPC: G06F13/42 , G06F9/30

CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Abstract translation: 串行数据链路在链路初始化期间进行调整。链路的适应包括从远程代理接收伪随机二进制序列（PRBS），分析PRBS以识别数据链路的特性，以及生成描述特征的度量数据。

34.

发明授权
High performance interconnect physical layer 有权

公开(公告)号：US11080212B2

公开(公告)日：2021-08-03

申请号：US16835241

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship

IPC: G06F13/42 , G06F13/16 , G06F1/12 , G06F13/40 , H04L12/933 , H04L12/741

Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.

35.

发明申请
HIGH PERFORMANCE INTERCONNECT 有权

公开(公告)号：US20210117350A1

公开(公告)日：2021-04-22

申请号：US17134242

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta

IPC: G06F13/22 , H04L12/933 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

36.

发明授权
High performance interconnect physical layer 有权

公开(公告)号：US10909055B2

公开(公告)日：2021-02-02

申请号：US16525454

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Ashish Gupta

IPC: G06F13/22 , H04L12/933 , G06F13/42 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46

Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.