公开(公告)号：US09680472B2

公开(公告)日：2017-06-13

申请号：US15182486

申请日：2016-06-14

Applicant: INTEL CORPORATION

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

公开(公告)号：US09633716B2

公开(公告)日：2017-04-25

申请号：US14989762

申请日：2016-01-06

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C8/08 ,  G11C11/417 ,  G11C7/12 ,  G11C8/10 ,  G11C11/418 ,  G11C13/00 ,  G11C5/14 ,  G11C29/02 ,  G11C11/412 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US09621163B2

公开(公告)日：2017-04-11

申请号：US14569569

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Carlos Tokunaga ,  James W. Tschanz

IPC: H03L5/00 ,  H03K19/0175

CPC classification number: H03K19/017509

Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.

公开(公告)号：US20160379695A1

公开(公告)日：2016-12-29

申请号：US14750670

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Ashoke Ravi ,  Dinesh Somasekhar ,  Ganesh Balamurugan ,  Sudip Shekhar ,  Tawfiq Musah ,  Tzu-Chien Hsueh

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/161 ,  G05F3/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H03H11/22 ,  H03K3/356104 ,  H03K19/018557 ,  H03K19/018585 ,  H03M1/12 ,  H03M1/362 ,  H03M1/66 ,  H03M1/765 ,  H04L25/00

Abstract: Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (Mils). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

Abstract translation: 实施例包括耦合在信号路径上的电阻器，其包括一个或多个电阻性存储器元件，诸如一个或多个磁性隧道结（Mils）。 电阻式存储器元件的电阻可以被数字可修整以调节电阻器在信号路径上的电阻。 电阻器可以并入到模拟或混合信号电路中，以在信号路径上传递模拟信号。 可以描述和要求保护其他实施例。

公开(公告)号：US09385722B2

公开(公告)日：2016-07-05

申请号：US14553934

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。 在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。 可以描述和要求保护其他实施例。

公开(公告)号：US20160141022A1

公开(公告)日：2016-05-19

申请号：US14830679

申请日：2015-08-19

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah ,  James W. Tschanz ,  Bibiche M. Geuskens ,  Vivek K. De

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/413

Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Abstract translation: 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到所述第一供应节点和第二供应节点的功率设备，所述第二供应节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。