公开(公告)号：US20250096178A1

公开(公告)日：2025-03-20

申请号：US18969889

申请日：2024-12-05

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US12003023B2

公开(公告)日：2024-06-04

申请号：US16258573

申请日：2019-01-26

Applicant: INTEL CORPORATION

Inventor： Zhenguo Jiang ,  Omkar Karhade ,  Srichaitra Chavali ,  Zhichao Zhang ,  Jimin Yao ,  Stephen Smith ,  Xiaoqian Li ,  Robert Sankman

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/38

CPC classification number: H01Q1/38 ,  H01L21/56 ,  H01L24/26 ,  H01Q1/2283 ,  H05K2201/10098

Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.

公开(公告)号：US11735552B2

公开(公告)日：2023-08-22

申请号：US16451754

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sergio Antonio Chan Arguedas ,  Jimin Yao ,  Chandra Mohan Jha

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/562 ,  H01L2224/1713 ,  H01L2224/17051 ,  H01L2224/17163 ,  H01L2224/17181 ,  H01L2224/17519

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20220181227A1

公开(公告)日：2022-06-09

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20220165686A1

公开(公告)日：2022-05-26

申请号：US17669265

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Kyle Yazzie ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H05K3/10 ,  B29C70/68 ,  H01L21/48 ,  H01L23/544 ,  H01L23/58

Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

公开(公告)号：US11322455B2

公开(公告)日：2022-05-03

申请号：US15845990

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Kyle Yazzie ,  Shawna M. Liff

IPC: H01L23/498 ,  H01L23/00 ,  H05K3/10 ,  B29C70/68 ,  H01L21/48 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  B29L31/34 ,  B29K63/00

Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

公开(公告)号：US20220020716A1

公开(公告)日：2022-01-20

申请号：US17488174

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US20190228988A1

公开(公告)日：2019-07-25

申请号：US16373615

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Eric Li ,  Shawna Liff

IPC: H01L21/56 ,  H01L23/31

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.

公开(公告)号：US20190074199A1

公开(公告)日：2019-03-07

申请号：US16083611

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sergio A. Chan Arguedas ,  Joshua D. Heppner ,  Jimin Yao

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.