公开(公告)号：US20140156923A1

公开(公告)日：2014-06-05

申请号：US13690523

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/406

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US10522207B2

公开(公告)日：2019-12-31

申请号：US15665143

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

公开(公告)号：US10121532B2

公开(公告)日：2018-11-06

申请号：US15640250

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/22 ,  G11C11/4093 ,  G11C29/52 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/04

Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

公开(公告)号：US09984737B2

公开(公告)日：2018-05-29

申请号：US15354200

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C7/08

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US09953694B2

公开(公告)日：2018-04-24

申请号：US15174946

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G06F3/06 ,  G11C14/00

CPC classification number: G11C11/40618 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C14/0009

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

公开(公告)号：US20170365329A1

公开(公告)日：2017-12-21

申请号：US15640250

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. Halbert

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C11/4076 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

公开(公告)号：US09721640B2

公开(公告)日：2017-08-01

申请号：US15184944

申请日：2016-06-16

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

公开(公告)号：US09536588B2

公开(公告)日：2017-01-03

申请号：US15181358

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC: G11C16/24 ,  G11C11/406 ,  G11C11/409 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Abstract translation: 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US20160283318A1

公开(公告)日：2016-09-29

申请号：US14670413

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Bill Nale ,  Kuljit S. Bains ,  John B. Halbert

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Abstract translation: 存储器子系统中的错误校正包括在执行内部错误检测和校正之后产生内部校验位的存储器件，以及向内存控制器提供内部校验位。 存储器件执行内部错误检测以响应于来自存储器控制器的读取请求来检测读取数据中的错误。 如果在读取的数据中检测到错误，则存储器件选择性地执行内部纠错。 在执行内部错误检测和校正之后，存储器件产生指示读取数据的错误向量的校验位，并且响应于读取请求将校验位与读取的数据提供给存储器控制器。 存储器控制器可以将校验位应用于存储器件外部的纠错。

公开(公告)号：US20160225434A1

公开(公告)日：2016-08-04

申请号：US15011286

申请日：2016-01-29

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G11C7/10 ,  G06F12/06

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。