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公开(公告)号：US08812792B2
公开(公告)日：2014-08-19
申请号：US14033463
申请日：2013-09-21
Applicant: Intel Corporation
Inventor： Quinn A. Jacobson , Anne W. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Shinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
CPC classification number: G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。
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公开(公告)号：US11061807B2
公开(公告)日：2021-07-13
申请号：US16235489
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Beeman Strong , Matthew C. Merten , Jason Agron
Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.
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公开(公告)号：US20180253370A1
公开(公告)日：2018-09-06
申请号：US15972390
申请日：2018-05-07
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US20180004628A1
公开(公告)日：2018-01-04
申请号：US15201405
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Beeman C. Strong , Matthew C. Merten , Lee W. Baugh
IPC: G06F11/36 , G06F9/30 , G06F12/0875
CPC classification number: G06F11/3648 , G06F9/3004 , G06F9/30145 , G06F9/3017 , G06F9/3877 , G06F11/3476 , G06F11/3636 , G06F12/0875 , G06F2212/452
Abstract: There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.
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Patent Agency Ranking
公开(公告)号：US20170371769A1
公开(公告)日：2017-12-28
申请号：US15194881
申请日：2016-06-28
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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公开(公告)号：US09746903B2
公开(公告)日：2017-08-29
申请号：US14823994
申请日：2015-08-11
Applicant: Intel Corporation
Inventor： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
CPC classification number: G06F1/3243 , Y02D10/152
Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
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公开(公告)号：US09733937B2
公开(公告)日：2017-08-15
申请号：US13843305
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Bratin Saha , Matthew C. Merten , Per Hammarlund
CPC classification number: G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/526 , G06F2209/521
Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
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公开(公告)号：US20160266992A1
公开(公告)日：2016-09-15
申请号：US14998055
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
CPC classification number: G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
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公开(公告)号：US20160203019A1
公开(公告)日：2016-07-14
申请号：US14998047
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
CPC classification number: G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
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