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公开(公告)号：US09910475B2
公开(公告)日：2018-03-06
申请号：US14580553
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
CPC classification number: G06F1/3206 , G06F11/3024 , G06F11/3055 , G06F11/348 , G06F2201/86
Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.
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公开(公告)号：US20180060078A1
公开(公告)日：2018-03-01
申请号：US15672254
申请日：2017-08-08
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V, Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
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公开(公告)号：US20170149554A1
公开(公告)日：2017-05-25
申请号：US14950319
申请日：2015-11-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Ernest Knoll , Ofer Nathan , Michael Mishaeli , Krishnakanth V. Sistla , Ariel Sabba , Shani Rehana , Ariel Szapiro , Tsvika Kurts , Ofer Levy
CPC classification number: H04L7/0331 , G06F1/08 , G06F1/10 , G06F1/324 , H04L7/0025 , H04L7/005 , Y02D10/126
Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
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公开(公告)号：US20170068298A1
公开(公告)日：2017-03-09
申请号：US15354018
申请日：2016-11-17
Applicant: INTEL CORPORATION
Inventor： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/3287 , G06F9/22 , Y02D10/171
Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A system on chip (SoC) includes a first functional unit, a second functional unit, and local power gate (LPG) hardware coupled to the first functional unit and the second functional unit. The LPG hardware is to power gate the first functional unit according to local power states of the LPG hardware. The second functional unit decodes a first instruction to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The second functional unit monitors a current local power state of the LPG hardware, selects a code path based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the first functional unit and continues execution of the first power-aware operation without waiting for the first functional unit to be powered up.
Abstract translation: 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 片上系统（SoC）包括耦合到第一功能单元和第二功能单元的第一功能单元，第二功能单元和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为第一个功能单元供电。 第二功能单元解码执行指定长度的第一功率感知操作的第一指令，包括计算用于执行的执行代码路径。 第二功能单元监视LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择代码路径，并向LPG硬件发出提示，以启动第一个功能 并且继续执行第一功率感知操作，而不等待第一功能单元被加电。
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公开(公告)号：US09396056B2
公开(公告)日：2016-07-19
申请号：US14214910
申请日：2014-03-15
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
CPC classification number: G06F11/079 , G06F11/0721 , G06F11/073
Abstract: In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.
Abstract translation: 在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障， 更多的故障抑制位。
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Patent Agency Ranking
公开(公告)号：US12189479B2
公开(公告)日：2025-01-07
申请号：US17993591
申请日：2022-11-23
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US20210357214A1
公开(公告)日：2021-11-18
申请号：US17334901
申请日：2021-05-31
Applicant: Intel Corporation
Inventor： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.
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公开(公告)号：US11048587B2
公开(公告)日：2021-06-29
申请号：US16292085
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US10990395B2
公开(公告)日：2021-04-27
申请号：US16666111
申请日：2019-10-28
Applicant: Intel Corporation
Inventor： Alexander Gendler , Eliezer Weissmann , Michael Mishaeli
Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.
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公开(公告)号：US10345889B2
公开(公告)日：2019-07-09
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
IPC: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/07
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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