公开(公告)号：US20190310944A1

公开(公告)日：2019-10-10

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US10296457B2

公开(公告)日：2019-05-21

申请号：US15474654

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Rajat Agarwal

IPC: G06F12/0811 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1027

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

公开(公告)号：US20190095332A1

公开(公告)日：2019-03-28

申请号：US15718071

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Rajat Agarwal

IPC: G06F12/0862 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/0817 ,  G06F12/1009

CPC classification number: G06F12/0877 ,  G06F12/0822 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/602 ,  G06F2212/621

Abstract: Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

公开(公告)号：US09691505B2

公开(公告)日：2017-06-27

申请号：US14670412

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Rajat Agarwal

IPC: G11C29/42 ,  G06F3/06 ,  G11C29/44 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/42 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

公开(公告)号：US20160284424A1

公开(公告)日：2016-09-29

申请号：US14670412

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debaleena Das ,  Rajat Agarwal

IPC: G11C29/42 ,  G06F3/06 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

Abstract translation: 存储器子系统中的误差校正包括确定误差是否是瞬态误差或持续性误差，以及基于误差类型调整ECC（错误检查和校正）的方法。 错误的类型可以通过内置的自检来确定。 如果错误是持续错误，则存储器控制器可以在擦除模式下执行，包括在应用ECC校正算法之前校正对所识别的错误位置的擦除。 否则，如果错误是瞬态的，则存储器控制器可以通过应用ECC校正算法执行标准的全ECC校正。

公开(公告)号：US12238221B2

公开(公告)日：2025-02-25

申请号：US17542842

申请日：2021-12-06

Applicant: INTEL CORPORATION

Inventor： David M. Durham ,  Rajat Agarwal ,  Siddhartha Chhabra ,  Sergej Deutsch ,  Karanvir S. Grewal ,  Ioannis T. Schoinas

IPC: H04L9/32 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0886 ,  G06F12/14 ,  G06F21/78 ,  G06F21/79 ,  G11C29/52 ,  H04L9/06 ,  H04L9/08 ,  G11C29/44

Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

公开(公告)号：US12124371B2

公开(公告)日：2024-10-22

申请号：US17214356

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Rajat Agarwal

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0895

CPC classification number: G06F12/0815 ,  G06F12/0895 ,  G06F2212/608

Abstract: An apparatus and method to reduce bandwidth and latency associated with probabilistic caches. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data, one or more of the cores to generate a request for a first cache line; a cache controller comprising cache lookup logic to determine a first way of a cache in which to search for the first cache line based on a first set of tag bits comprising one or more bits associated with the first cache line; the cache lookup logic to compare a second set of tag bits of the first cache line with a third set of tag bits of an existing cache line stored in the first way, wherein if the second set of tag bits and the third set of tag bits to not match, then the cache lookup logic to determine that the first cache line is not in the first way and to compare a fourth set of tag bits of the first cache line with a fifth set of tag bits of the existing cache line, wherein responsive to a match between the fourth set of tag bits and the fifth set of tag bits, the cache lookup logic to determine that the first cache line is stored in a second way and to responsively read the first cache line from the second way.

公开(公告)号：US12066888B2

公开(公告)日：2024-08-20

申请号：US17944352

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David M. Durham ,  Karanvir Grewal ,  Rajat Agarwal

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0673

Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.

公开(公告)号：US11995006B2

公开(公告)日：2024-05-28

申请号：US17559258

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  Karanvir Grewal ,  David M. Durham ,  Rajat Agarwal

IPC: G06F21/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/0853 ,  G06F12/14

CPC classification number: G06F12/1466 ,  G06F11/0772 ,  G06F11/1068 ,  G06F12/0853 ,  G06F12/1408

Abstract: A method comprises generating, for a cacheline, a first tag and a second tag, the first tag and the second tag generated as a function of user data stored and metadata in the cacheline stored in a first memory device, and a multiplication parameter derived from a secret key, storing the user data, the metadata, the first tag and the second tag in the first cacheline of the first memory device; generating, for the cacheline, a third tag and a fourth tag, the third tag and the fourth tag generated as a function of the user data stored and metadata in the cacheline stored in a second memory device, and the multiplication parameter; storing the user data, the metadata, the third tag and the fourth tag in the corresponding cache line of the second memory device; receiving, from a requesting device, a read operation directed to the cacheline; and using the first tag, the second tag, the third tag, and the fourth tag to determine whether a read error occurred during the read operation.

公开(公告)号：US11966286B2

公开(公告)日：2024-04-23

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

CPC classification number: G06F11/1044 ,  G06F11/1072 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.