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    Inexpensive Electrode Materials to Facilitate Rutile Phase Titanium Oxide
    31.
    发明申请
    Inexpensive Electrode Materials to Facilitate Rutile Phase Titanium Oxide 有权
    廉价的电极材料促进金红石相氧化钛

    公开(公告)号：US20130072015A1

    公开(公告)日：2013-03-21

    申请号：US13675852

    申请日：2012-11-13

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L21/285

    CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

    Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

    Enhanced work function layer supporting growth of rutile phase titanium oxide
    33.
    发明授权
    Enhanced work function layer supporting growth of rutile phase titanium oxide 有权
    增强功能层支持金红石相氧化钛的生长

    公开(公告)号：US08975147B2

    公开(公告)日：2015-03-10

    申请号：US13708035

    申请日：2012-12-07

    Applicant: Intermolecular, Inc.

    Inventor： Xiangxin Rui ,  Hanhong Chen ,  Pragati Kumar ,  Sandra G. Malhotra

    IPC: H01L21/02 ,  C01G23/047 ,  C23C16/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  H01L49/02 ,  H01L27/108 ,  B82Y99/00

    CPC classification number: H01L21/02 ,  B82Y99/00 ,  C01G23/047 ,  C01P2002/72 ,  C23C16/0272 ,  C23C16/34 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02186 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/40

    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

    Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

    DRAM MIM capacitor using non-noble electrodes
    34.
    发明授权
    DRAM MIM capacitor using non-noble electrodes 有权
    DRAM MIM电容器采用非贵金属电极

    公开(公告)号：US08969169B1

    公开(公告)日：2015-03-03

    申请号：US14033326

    申请日：2013-09-20

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

    IPC: H01L21/00 ,  H01L49/02

    CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

    Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

    Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。

    High work function, manufacturable top electrode
    36.
    发明授权
    High work function, manufacturable top electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US08847397B2

    公开(公告)日：2014-09-30

    申请号：US13737263

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

    Semiconductor stacks including catalytic layers
    37.
    发明授权
    Semiconductor stacks including catalytic layers 有权
    包括催化层的半导体堆叠

    公开(公告)号：US08581319B2

    公开(公告)日：2013-11-12

    申请号：US13738901

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L29/94

    CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

    Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

    Method for Producing MIM Capacitors with High K Dielectric Materials and Non-Noble Electrodes
    38.
    发明申请
    Method for Producing MIM Capacitors with High K Dielectric Materials and Non-Noble Electrodes 有权
    用高K绝缘材料和非贵重电极生产MIM电容器的方法

    公开(公告)号：US20130285205A1

    公开(公告)日：2013-10-31

    申请号：US13902679

    申请日：2013-05-24

    Applicant: Elpida Memory, Inc. ,  INTERMOLECULAR, INC.

    Inventor： Hanhong Chen ,  Pragati Kumar

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L28/40

    Abstract: A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.

    Abstract translation: 公开了一种通过掺杂制造金属 - 绝缘体 - 金属（MIM）电容器堆叠以实现低电流泄漏和低等效氧化物厚度的方法。 高K电介质材料沉积在非贵金属电极上; 电介质材料掺杂有IIA族的氧化物。 掺杂剂增加了金属/绝缘体界面的势垒高度，并且中和了介电材料中的自由电子，从而降低了MIM电容器的漏电流。 电极也可以掺杂以增加功函数，同时保持金红石晶体结构。 该方法从而增强了DRAM MIM电容器的性能。

    System and Method for Step Coverage Measurement
    39.
    发明申请
    System and Method for Step Coverage Measurement 有权
    步骤覆盖测量的系统和方法

    公开(公告)号：US20130272496A1

    公开(公告)日：2013-10-17

    申请号：US13914848

    申请日：2013-06-11

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Edward Haywood ,  Pragati Kumar

    IPC: G01N23/223

    CPC classification number: G01N23/223 ,  H01L22/12

    Abstract: Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.

    Abstract translation: 确定沉积在3D晶片上的薄膜的未知步骤覆盖包括将包括沉积在其上的第一膜的平面晶片暴露于X射线辐射以产生第一荧光辐射; 检测第一荧光辐射; 测量平面晶片上的XRF数量; 创建平面晶片的XRF模型; 提供包括槽的3D晶片的一部分和沉积在其上的第二膜; 确定所述3D晶片的所述部分和所述平面晶片之间的乘数; 将3D晶片的部分暴露于X射线辐射以产生第二荧光辐射; 检测第二荧光辐射; 测量3D晶片部分上的XRF数量; 计算3D晶片的部分的台阶覆盖; 以及基于所述3D晶片的所述部分的台阶覆盖来确定所述3D晶片的均匀性。

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