公开(公告)号：US20150064873A1

公开(公告)日：2015-03-05

申请号：US14527276

申请日：2014-10-29

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20140264747A1

公开(公告)日：2014-09-18

申请号：US14137003

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract translation: 电介质层可以实现类似于具有设置在两个电介质层之间的导电层的基极电介质层的结晶取向。 通过提供具有与基底电介质层相似的晶体结构和晶格参数的导电层，晶体取向可以从基极介电层承载在导电层上以影响电介质层。 该方法可以用于形成各向异性介电材料的电容器结构，沿着高介电常数的方向。

公开(公告)号：US08835310B2

公开(公告)日：2014-09-16

申请号：US13725701

申请日：2012-12-21

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L21/4763 ,  H01L49/02

CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

公开(公告)号：US20140166107A1

公开(公告)日：2014-06-19

申请号：US13714274

申请日：2012-12-13

Applicant: INTERMOLECULAR, INC.

Inventor： Mankoo Lee ,  Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L31/0264 ,  H01L31/18

CPC classification number: H01L31/056 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/52 ,  Y02E10/541

Abstract: Methods for improving the efficiency of solar cells are disclosed. A solar cell consistent with the present disclosure includes a back contact metal layer disposed on a substrate. The solar cell also includes an electron reflector material(s) layer formed on the back contact metal layer and an absorber material(s) layer disposed on the electron reflector material(s) layer. In addition, the solar cell includes a buffer material(s) layer formed on the absorber material(s) layer wherein the electron reflector material(s) layer, absorber material(s) layer, and buffer material(s) layer form a pn junction within the solar cell. Furthermore, a TCO material(s) layer is formed on the buffer material(s) layer. In addition, the front contact layer is formed on the TCO material(s) layer.

Abstract translation: 公开了提高太阳能电池效率的方法。 符合本公开的太阳能电池包括设置在基板上的背接触金属层。 太阳能电池还包括形成在背接触金属层上的电子反射器材料层和设置在电子反射器材料层上的吸收体材料层。 此外，太阳能电池包括形成在吸收材料层上的缓冲材料层，其中电子反射器材料层，吸收材料层和缓冲材料层形成pn 太阳能电池内的接头。 此外，在缓冲材料层上形成TCO材料层。 此外，前接触层形成在TCO材料层上。

公开(公告)号：US09177916B1

公开(公告)日：2015-11-03

申请号：US14553354

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L23/52 ,  H01L23/528

CPC classification number: H01L27/2481 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/73 ,  H01L23/528 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are resistive switching memory cells having selectors and methods of fabricating such cells. A selector may be disposed between an electrode and resistive switching layer. The selector is configured to undergo an electrical breakdown when a voltage applied to the selector exceeds a selected threshold. The selector is formed from amorphous silicon doped with fluorine. The concentration of fluorine may be between about 0.01% atomic and 3% atomic, such as about 1% atomic. Amorphous silicon has a larger band gap than, for example, crystalline silicon and, therefore, has a lower leakage. Dangling bond and weak bond states appearing in the mid-gap position of amorphous silicon are eliminated by adding fluorine. Fluorine binds to and passivates defects. In some embodiments, a fluorine reservoir is positioned in a low current density region of the memory cell to counter diffusion of fluorine from the selector into other components.

Abstract translation: 提供了具有选择器的电阻式开关存储单元和制造这种单元的方法。 选择器可以设置在电极和电阻式开关层之间。 选择器被配置为当施加到选择器的电压超过所选择的阈值时经历电击穿。 选择器由掺杂氟的非晶硅形成。 氟的浓度可以在约0.01％原子和3％原子之间，例如约1％的原子。 无定形硅具有比例如晶体硅更大的带隙，因此具有较低的泄漏。 通过添加氟来消除出现在非晶硅中间位置的悬挂键和弱键状态。 氟结合并钝化缺陷。 在一些实施例中，氟储存器定位在存储器单元的低电流密度区域中，以防止氟从选择器到其它部件的扩散。

公开(公告)号：US20150313046A1

公开(公告)日：2015-10-29

申请号：US14259455

申请日：2014-04-23

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

IPC: H05K9/00 ,  H01L39/24 ,  H01L39/02

CPC classification number: H01B12/02 ,  H01L39/22 ,  H01L39/24 ,  Y10S505/704 ,  Y10S505/706

Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

Abstract translation: 提供超导电路，操作这些超导电路的方法以及确定用于操作这些超导电路的处理条件的方法。 超导电路包括超导元件，导电元件和设置在超导元件和导电元件之间的介电元件。 导电元件可以是另一种超导元件，谐振元件或导电壳体。 在超导元件的操作期间，在超导元件和导电元件之间施加直流（DC）电压。 DC电压的这种应用降低了介电元件的平均微波吸收。 在一些实施例中，当首先施加DC电压时，微波吸收可以最初升高然后降低到无电压吸收水平以下。 直流电压电平可以通过在不同的直流电压电平下测试超导电路并选择具有最低微波吸收的电路来确定。

公开(公告)号：US20150187865A1

公开(公告)日：2015-07-02

申请号：US14145117

申请日：2013-12-31

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L29/66181 ,  H01L29/94

Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

Abstract translation: 提供用于集成电路的电容器堆叠以及制造这些堆叠的方法。 电容器堆叠包括电介质层和一个或两个内部电极层，例如正的内部电极层和负的内部电极层。 内部电极层直接与介电层接触。 堆叠还可以包括外部电极层。 内部电极层是化学稳定的或弱的化学不稳定的，同时基于相应的相图与介电层接触。 此外，正内电极层的电子亲和力可能小于电介质层的电子亲和力。 负的内电极层的电子亲和力和带隙的总和可以小于电介质层的电子亲和力。 在一些实施例中，内部电极层由重掺杂的半导体材料形成，例如砷化镓或砷化镓铝。

公开(公告)号：US20150179915A1

公开(公告)日：2015-06-25

申请号：US14138909

申请日：2013-12-23

Applicant: INTERMOLECULAR, INC.

Inventor： Frank Greer ,  Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

IPC: H01L39/24 ,  C23C16/24 ,  C23C16/50 ,  H01L39/12

CPC classification number: C23C16/50 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02123 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76891 ,  H01L23/53285 ,  H01L23/5329 ,  H01L27/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.

Abstract translation: 制造用于超导电子器件（例如，非晶硅，氧化硅或氮化硅）的电介质，通过在整个整个层中的氟钝化降低损耗角正切。 将荧光（气体或等离子体）连续地或作为一系列脉冲注入到处理室中，同时电介质通过化学气相沉积在衬底上形成。 为了进一步减少缺陷，可以从包括多个共键合的硅原子的硅前体（例如乙硅烷或丙硅烷）沉积硅。

公开(公告)号：US09019744B2

公开(公告)日：2015-04-28

申请号：US13728739

申请日：2012-12-27

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/147 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1633

Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Abstract translation: 适用于存储器件应用的转向元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，操纵元件可以包括第一电极，第二电极和夹在两个电极之间的渐变电介质层。 渐变电介质层可以包括从第一电极到第二电极的不同组成。 带隙的顶部和/或底部的分级能级可以是梯度介电层组成的结果，和/或电极的功函数可以被配置为抑制断开的隧道和热离子电流 和/或最大化导通状态和转向元件断开状态下的隧道和热离子电流的比例。

公开(公告)号：US09012260B2

公开(公告)日：2015-04-21

申请号：US14527276

申请日：2014-10-29

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L29/82 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。