公开(公告)号：US09536750B1

公开(公告)日：2017-01-03

申请号：US14870932

申请日：2015-09-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract translation: 制造半导体器件的方法包括在衬底上设置第一硬掩模（HM），非晶硅和第二HM; 在第二HM上设置氧化物和中性层; 去除所述氧化物和中性层的一部分以暴露所述第二HM的一部分; 通过选择性地回填聚合物形成引导图案; 在引导图案上形成自组装嵌段共聚物（BCP）; 去除BCP的一部分以形成蚀刻模板; 将图案从所述模板转移到衬底中并且形成具有不同材料和高度的两种类型的HM堆叠的均匀硅片阵列; 填充氧化物，然后平坦化; 用第三HM材料选择性地去除和更换较高的HM堆叠; 平坦化表面并暴露两个HM堆叠; 并选择性地去除下面的较短的HM堆叠和硅片。

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US11990470B2

公开(公告)日：2024-05-21

申请号：US17483958

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L27/08 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L28/60

Abstract: An apparatus includes a first plate, a second plate, a third plate, a ferroelectric dielectric, and a paraelectric dielectric. The ferroelectric dielectric is between the first plate and the second plate such that the first plate, the ferroelectric dielectric, and the second plate form a first capacitor. The paraelectric dielectric is between the second plate and the third plate such that the second plate, the paraelectric dielectric, and the third plate form a second capacitor.

公开(公告)号：US20240072035A1

公开(公告)日：2024-02-29

申请号：US17900203

申请日：2022-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Indira Seshadri ,  Cheng Chi ,  Albert M. Chu

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/11866

Abstract: A circuit is presented including a plurality of cells separated by a plurality of cell boundaries and at least one curved gate cut region disposed over a curved cell boundary of the plurality of cell boundaries. The at least one curved gate cut region separates a reduced active area from a widened active area. The reduced active area is defined above the curved cell boundary and the widened active area is defined below the curved cell boundary.

公开(公告)号：US11916014B2

公开(公告)日：2024-02-27

申请号：US17482874

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

公开(公告)号：US20240006346A1

公开(公告)日：2024-01-04

申请号：US17854125

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Takashi Ando ,  REINALDO VEGA ,  Praneet Adusumilli

IPC: H01L23/00

CPC classification number: H01L23/573

Abstract: An integrated circuit includes a semiconductor substrate; a logic area, located outward of the semiconductor substrate; and a physically unclonable function (PUF) area, located outward of the semiconductor substrate. The logic area includes a plurality of logic metal-insulator-metal decoupling capacitors with at least three plates. The PUF area includes a plurality of PUF metal-insulator-metal capacitors with at least three plates. Shorts and opens are avoided in the logic area, while the PUF metal-insulator-metal capacitors exhibit deliberately-introduced shorts and opens that function as a PUF.

公开(公告)号：US20230422461A1

公开(公告)日：2023-12-28

申请号：US17808178

申请日：2022-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： REINALDO VEGA ,  Takashi Ando ,  Praneet Adusumilli ,  David Wolpert ,  Cheng Chi

IPC: H01L27/11 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L27/1104 ,  H01L23/5286 ,  H01L28/40

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

公开(公告)号：US11527647B2

公开(公告)日：2022-12-13

申请号：US17139053

申请日：2020-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/12

Abstract: A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

公开(公告)号：US11502252B2

公开(公告)日：2022-11-15

申请号：US16952203

申请日：2020-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/063 ,  G06N3/04

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.

公开(公告)号：US11424362B2

公开(公告)日：2022-08-23

申请号：US17118752

申请日：2020-12-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/07 ,  H01L29/66

Abstract: A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.