公开(公告)号：US10249622B2

公开(公告)日：2019-04-02

申请号：US15602740

申请日：2017-05-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith E. Fogel ,  Sivananda K. Kanakasabapathy ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

公开(公告)号：US10229921B2

公开(公告)日：2019-03-12

申请号：US15424278

申请日：2017-02-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11507 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

公开(公告)号：US20190035787A1

公开(公告)日：2019-01-31

申请号：US15992507

申请日：2018-05-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L27/092 ,  H01L27/112 ,  H01L29/08 ,  H01L27/098 ,  H01L27/06 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

公开(公告)号：US10170469B2

公开(公告)日：2019-01-01

申请号：US15498669

申请日：2017-04-27

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522

Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.

公开(公告)号：US10170464B2

公开(公告)日：2019-01-01

申请号：US14732174

申请日：2015-06-05

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/8252

Abstract: Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a buffer layer of the semiconductor device. For instance, a semiconductor device includes a buffer layer disposed on a substrate, a channel layer disposed on the buffer layer, and a buried resistor disposed within the buffer layer. The buffer and channel layers may be formed of compound semiconductor materials such as III-V compound semiconductor materials. Utilizing the buffer layer of a compound semiconductor structure to form buried resistors provides a space-efficient design with increased integration density since the resistors do not have to occupy a large amount of space on the active surface of a semiconductor integrated circuit chip.

公开(公告)号：US20180350953A1

公开(公告)日：2018-12-06

申请号：US16040149

申请日：2018-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/768 ,  H01L21/761 ,  H01L21/311 ,  H01L21/225

Abstract: A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.

公开(公告)号：US10115801B1

公开(公告)日：2018-10-30

申请号：US15856986

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/423 ,  H01L29/73

Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

公开(公告)号：US10090307B2

公开(公告)日：2018-10-02

申请号：US15298733

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/108 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L49/02

Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

公开(公告)号：US10083882B2

公开(公告)日：2018-09-25

申请号：US15608558

申请日：2017-05-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Sanghoon Lee

IPC: H01L21/76 ,  H01L21/84 ,  H01L21/308 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3081 ,  H01L21/31056 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78696

Abstract: A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a orientation wherein the hard mask is oriented in the direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

公开(公告)号：US20180269289A1

公开(公告)日：2018-09-20

申请号：US15459608

申请日：2017-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/735 ,  H01L29/66 ,  H01L23/66

CPC classification number: H01L29/1008 ,  H01L23/66 ,  H01L29/0649 ,  H01L29/6625 ,  H01L29/735

Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.