公开(公告)号：US11450560B2

公开(公告)日：2022-09-20

申请号：US16140398

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Kaladhar Radhakrishnan ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L21/768

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a first surface and an opposing second surface, wherein the first die is in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, wherein the magnetic core inductor may include a first conductive pillar at least partially surrounded by a magnetic material, and a second conductive pillar coupled to the first conductive pillar; and a second die having a first surface and an opposing second surface, wherein the second die is in a second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20220093492A1

公开(公告)日：2022-03-24

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H05K1/11 ,  H01L23/538 ,  H01L23/532

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US11211866B2

公开(公告)日：2021-12-28

申请号：US16642268

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Kaladhar Radhakrishnan ,  Beomseok Choi ,  Krishna Bharath ,  Michael J. Hill

IPC: H02M3/158 ,  G01R19/165 ,  G05F1/46 ,  H01F21/02 ,  H02M1/00 ,  H02M3/156

Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.

公开(公告)号：US20210183846A1

公开(公告)日：2021-06-17

申请号：US17185504

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： Jeffory L. Smalley ,  Thomas Holden ,  Russell J. Wunderlich ,  Farzaneh Yahyaei-Moayyed ,  Mohanraj Prabhugoud ,  Horthense Delphine Tamdem ,  Vijaya Boddu ,  Kaladhar Radhakrishnan ,  Timothy Glen Hanna ,  Krishna Bharath ,  Judy Amanor-Boadu ,  Mark A. Schmisseur ,  Srikant Nekkanty ,  Luis E. Rosales Galvan

IPC: H01L25/18 ,  H01L23/498 ,  H01R12/71

Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.

公开(公告)号：US20200251448A1

公开(公告)日：2020-08-06

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200098676A1

公开(公告)日：2020-03-26

申请号：US16140195

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/36

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die, having an active surface and an opposing backside surface, including a plurality of through silicon vias (TSVs); and an inductor including a first conductive pillar with a first end and an opposing second end, wherein the first end of the first conductive pillar is coupled to the backside surface of a first individual TSV; a second conductive pillar with a first end and an opposing second end, wherein the first end of the second conductive pillar is coupled to the backside surface of a second individual TSV, wherein the second end of the second conductive pillar is coupled to the second end of the first conductive pillar, and wherein the first and the second conductive pillars are at least partially surrounded in a magnetic material.

公开(公告)号：US20200005989A1

公开(公告)日：2020-01-02

申请号：US16024593

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Adel Elsherbini

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/02 ,  H01F41/04

Abstract: A microelectronics package comprising a package core and an inductor over the package core. The inductor comprises a dielectric over the package core. The dielectric comprises a curved surface opposite the package core. At least one conductive trace is adjacent to the package core. The at least one conductive trace is at least partially embedded within the dielectric and extends over the package core. A magnetic core cladding is over the dielectric layer and at least partially surrounding the conductive trace.

公开(公告)号：US12224252B2

公开(公告)日：2025-02-11

申请号：US17030121

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  William J. Lambert ,  Haifa Hariri ,  Siddharth Kulasekaran ,  Mathew Manusharow ,  Anne Augustine

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

公开(公告)号：US12062631B2

公开(公告)日：2024-08-13

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/09505 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11955426B2

公开(公告)日：2024-04-09

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6672

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.