公开(公告)号：US11646288B2

公开(公告)日：2023-05-09

申请号：US16635146

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Gianni Signorini ,  Veronica Sciriha ,  Thomas Wagner

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/15311 ,  H01L2924/19104

Abstract: In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

公开(公告)号：US20240405433A1

公开(公告)日：2024-12-05

申请号：US18328107

申请日：2023-06-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georg Seidemann ,  Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Tae Young Yang

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.

公开(公告)号：US11990408B2

公开(公告)日：2024-05-21

申请号：US16833169

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Jan Proschwitz

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/552

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/562 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/16227

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces.

公开(公告)号：US20230300975A1

公开(公告)日：2023-09-21

申请号：US17699211

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Jan Proschwitz ,  Sonja Koller ,  Thomas Wagner ,  Vishnu Prasad ,  Wolfgang Molzer

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L21/4803 ,  H01L23/13 ,  H01L25/0652 ,  H01L25/18 ,  H05K3/305 ,  H05K1/181 ,  H01L25/0657 ,  H01L24/16

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.

公开(公告)号：US20230090265A1

公开(公告)日：2023-03-23

申请号：US17991503

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US11270941B2

公开(公告)日：2022-03-08

申请号：US16349170

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Bernd Waidhas

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US11107763B2

公开(公告)日：2021-08-31

申请号：US16469113

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Andreas Wolter ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

公开(公告)号：US20190287904A1

公开(公告)日：2019-09-19

申请号：US16349170

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Bernd Waidhas

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US20190006318A1

公开(公告)日：2019-01-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F15/76 ,  H01L21/486 ,  H01L23/481 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1011 ,  H01L2225/1017 ,  H01L2225/1058

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.