公开(公告)号：US20190042112A1

公开(公告)日：2019-02-07

申请号：US15927042

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Sarvesh Varakabe Gangadhar ,  Feng Zhu ,  Xin Guo ,  Simon D. Ramage ,  Ning Wu ,  Robert E. Frickey, III

IPC: G06F3/06 ,  G11C16/34 ,  G06F11/30

Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.

公开(公告)号：US10095424B2

公开(公告)日：2018-10-09

申请号：US15228729

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： Wei Wu ,  Yi Zou ,  Jawad B. Khan ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G06F12/1009

Abstract: Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.

公开(公告)号：US10061516B2

公开(公告)日：2018-08-28

申请号：US14866192

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  David J. Pelster ,  Eric L. Hoffman

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C2211/5641

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

公开(公告)号：US09543019B2

公开(公告)日：2017-01-10

申请号：US13710913

申请日：2012-12-11

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G06F11/10 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F11/1048 ,  G11C11/5628

Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

Abstract translation: 方法，设备和制造品可以接收第一页数据并且校正第一页数据中的一个或多个错误以产生校正数据的页面。 然后可以用第二页数据和校正数据的页面发送程序命令，以编程存储器页面以存储第二页数据。

公开(公告)号：US09490018B2

公开(公告)日：2016-11-08

申请号：US14679574

申请日：2015-04-06

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P. Belgal

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/06 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C29/02 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

公开(公告)号：US09183091B2

公开(公告)日：2015-11-10

申请号：US13628356

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F9/445 ,  G06F11/14

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。

公开(公告)号：US12253911B2

公开(公告)日：2025-03-18

申请号：US17534944

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Xin Guo ,  Ravi Motwani ,  Donia Sebastian ,  Aaron Lutzker

IPC: G06F11/10 ,  G06F3/06 ,  G06F7/58 ,  G06F11/07

Abstract: Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

公开(公告)号：US20220083419A1

公开(公告)日：2022-03-17

申请号：US17534944

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Xin Guo ,  Ravi Motwani ,  Donia Sebastian ,  Aaron Lutzker

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  G06F7/58

Abstract: Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

公开(公告)号：US20210392083A1

公开(公告)日：2021-12-16

申请号：US17355915

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Shirish Bahirat ,  Anand Ramalingam ,  Solomon Sagar Albert Jayaraj ,  Fnu Sachin ,  Xin Guo

IPC: H04L12/851

Abstract: Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

公开(公告)号：US10956081B2

公开(公告)日：2021-03-23

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. Pelster ,  David B. Carlton ,  Mark Anthony Golez ,  Xin Guo ,  Aliasgar S. Madraswala ,  Sagar S. Sidhpura ,  Sagar Upadhyay ,  Neelesh Vemula ,  Yogesh B. Wakchaure ,  Ye Zhang

IPC: G06F3/06

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.