公开(公告)号：US20190244979A1

公开(公告)日：2019-08-08

申请号：US15929125

申请日：2019-04-18

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Yohei YAMAGUCHI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Hirokazu WATANABE ,  Marina SHIOKAWA

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L21/4763 ,  H01L21/465

CPC classification number: H01L27/1225 ,  G02F1/133305 ,  G02F1/13452 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G02F2202/10 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/465 ,  H01L21/47635 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1266 ,  H01L27/127 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A display device to improve reliability of the TFT of the oxide semiconductor, including: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor; a first gate insulating film is formed on the first oxide semiconductor, a gate electrode is formed on the first gate insulating film, an interlayer insulating film is formed over the gate electrode; the gate insulating film includes a first silicon oxide film, the gate electrode includes a first gate layer made of a second oxide semiconductor and a second gate layer made of metal or alloy; the interlayer insulating film has a first interlayer insulating film including a second silicon oxide film, and a second interlayer insulating film including a first aluminum oxide film on the first interlayer insulating film.

公开(公告)号：US20250113625A1

公开(公告)日：2025-04-03

申请号：US18897125

申请日：2024-09-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Masahiro WATABE

IPC: H01L31/119 ,  H01L25/04 ,  H01L31/02 ,  H01L31/0224

Abstract: A radiation detector according to an embodiment of the present invention includes: a transistor in which an oxide semiconductor layer is used in a channel of the transistor; a photoelectric converting layer connected to the transistor; a wavelength converting layer facing the photoelectric converting layer and capable of emitting visible light based on radioactive rays absorbed by the wavelength converting layer; and an oxide layer in contact with the oxide semiconductor layer between the transistor and the photoelectric converting layer, wherein a thickness of the oxide layer is 50 nm or less.

公开(公告)号：US20250048680A1

公开(公告)日：2025-02-06

申请号：US18898825

申请日：2024-09-27

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, an insulating layer over the substrate, a metal oxide layer over the insulating layer, and an oxide semiconductor layer over the metal oxide layer. The insulating layer includes a first region overlapping the metal oxide layer and a second region not overlapping the metal oxide layer. A hydrogen concentration of the first region is greater than a hydrogen concentration of the second region. A nitrogen concentration of the first region is greater than a nitrogen concentration of the second region.

公开(公告)号：US20250022929A1

公开(公告)日：2025-01-16

申请号：US18897128

申请日：2024-09-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer provided above an insulating surface, a gate insulating layer provided above the oxide semiconductor layer, and a gate electrode provided above the oxide semiconductor layer via the gate insulating layer, wherein the gate electrode has a titanium-containing layer and a conductive layer in order from the gate insulating layer side, the gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode, and a thickness of the titanium-containing layer is 50% or less than a thickness of the gate insulating layer in the first region.

公开(公告)号：US20240332429A1

公开(公告)日：2024-10-03

申请号：US18618022

申请日：2024-03-27

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device comprises a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; and a gate wiring on the gate insulating layer. The metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer, a second region overlapping the oxide semiconductor layer and not overlapping the gate wiring, and a third region overlapping the gate wiring and not overlapping the oxide semiconductor layer.

公开(公告)号：US20240332308A1

公开(公告)日：2024-10-03

申请号：US18597186

申请日：2024-03-06

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  H01L27/1274 ,  H01L29/7869 ,  H10K59/1213

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer. The interlayer insulating layer covers the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm.

公开(公告)号：US20240250091A1

公开(公告)日：2024-07-25

申请号：US18411028

申请日：2024-01-12

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/7869 ,  G02F1/1368

Abstract: A semiconductor device includes an oxide semiconductor layer including a polycrystalline structure, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer connected to the oxide semiconductor layer, and a second transparent conductive layer arranged in the same layer as the first transparent conductive layer and separated from the first transparent conductive layer, wherein crystallizability of the first transparent conductive layer is different from crystallizability of the second transparent conductive layer.

公开(公告)号：US20240097043A1

公开(公告)日：2024-03-21

申请号：US18456832

申请日：2023-08-28

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takay TAMARU

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a protective insulating layer. The gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The second region is in contact with the protective insulating layer. The oxide insulating layer includes a third region overlapping the gate electrode and a fourth region not overlapping the gate electrode and the oxide semiconductor layer. The fourth region is in contact with the gate insulating layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. Each of the source region, the drain region, and the second region contains an impurity. A hydrogen concentration of the second region is greater than a hydrogen concentration of the first region.

公开(公告)号：US20240057413A1

公开(公告)日：2024-02-15

申请号：US18230171

申请日：2023-08-04

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H10K59/131 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/1213

Abstract: A display device includes a display panel including a display portion having a plurality of pixels; and a sensor element disposed on a rear side of the display portion. The display portion has a first region overlapping the sensor element and a second region other than the first region in a plan view. Each of the plurality of pixels has a semiconductor device including a channel portion and a conductive portion made of an oxide semiconductor having a polycrystalline structure. Each of the plurality of pixels in the first region is connected by a first signal line comprising the same layer as the conductive portion, and each of the plurality of pixels in the second region is connected by a second signal line comprising a metal layer connected to the conductive portion.

公开(公告)号：US20230317834A1

公开(公告)日：2023-10-05

申请号：US18127679

申请日：2023-03-29

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L21/385 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/385 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7832

Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming a first metal oxide layer containing aluminum as a main component above a substrate; forming an oxide semiconductor layer above the first metal oxide layer; forming a gate insulating layer above the oxide semiconductor layer; forming a second metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the second metal oxide layer is formed above the gate insulating layer; removing the second metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.