公开(公告)号：US06788598B2

公开(公告)日：2004-09-07

申请号：US10448661

申请日：2003-05-30

Applicant: Ming-Cheng Chang ,  Tie-Jiang Wu ,  Jeng-Ping Lin ,  Tse-Main Kuo ,  Hsu-Cheng Fan

Inventor： Ming-Cheng Chang ,  Tie-Jiang Wu ,  Jeng-Ping Lin ,  Tse-Main Kuo ,  Hsu-Cheng Fan

IPC: G11C700

CPC classification number: H01L27/10861 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5004 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/10891 ,  H01L29/66181

Abstract: A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.

公开(公告)号：US20130075812A1

公开(公告)日：2013-03-28

申请号：US13239389

申请日：2011-09-22

Applicant: Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

Inventor： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC: H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract translation: 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US08395209B1

公开(公告)日：2013-03-12

申请号：US13239389

申请日：2011-09-22

Applicant: Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

Inventor： Hsin-Jung Ho ,  Jeng-Ping Lin ,  Neng-Tai Shih ,  Chang-Rong Wu ,  Chiang-Hung Lin ,  Chih-Huang Wu

IPC: H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract translation: 单面存取装置包括活动鳍片结构，其包括源极接触区域和通过它们之间的隔离区域彼此分离的漏极接触区域; 沟槽隔离结构，设置在所述有源鳍结构的一侧，其中所述沟槽隔离结构与所述源极接触区域和所述漏极接触区域之间的隔离区域相交; 侧壁门，其设置在所述隔离区域下方并且在所述有源鳍结构的另一侧与所述沟槽隔离结构相对，使得所述有源鳍结构被所述沟槽隔离结构和所述侧壁栅极夹持，其中所述侧壁门具有多指 与活跃的鳍结构互动; 以及在侧壁浇口和活性鳍结构之间的栅介质层。

公开(公告)号：US08343829B2

公开(公告)日：2013-01-01

申请号：US13171405

申请日：2011-06-28

Applicant: Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

Inventor： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract translation: 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US07759190B2

公开(公告)日：2010-07-20

申请号：US11925363

申请日：2007-10-26

Applicant: Neng-Tai Shih ,  Jeng-Ping Lin

Inventor： Neng-Tai Shih ,  Jeng-Ping Lin

IPC: H01L27/108

CPC classification number: H01L27/10867

Abstract: A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.

Abstract translation: 公开了一种存储器件的制造方法。 提供具有沟槽的衬底，其中包括沟槽电容器，导电柱，套环电介质层和顶部电介质层。 具有侧壁上的间隔物的栅极结构设置在衬底上并与沟槽相邻。 在轴环电介质层和栅极结构之间的基板上形成开口。 接下来，去除顶部电介质层和套环电介质层的一部分以暴露导电柱的一部分。 绝缘层沉积在栅极结构和暴露的导电柱上，填充开口。 蚀刻绝缘层以暴露基板和导电柱的电容器侧区域的一部分。 通过选择性沉积形成透射带，电连接基板的电容器侧区域和导电柱。

公开(公告)号：US20080251829A1

公开(公告)日：2008-10-16

申请号：US11925363

申请日：2007-10-26

Applicant: Neng-Tai Shih ,  Jeng-Ping Lin

Inventor： Neng-Tai Shih ,  Jeng-Ping Lin

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867

Abstract: A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.

Abstract translation: 公开了一种存储器件的制造方法。 提供具有沟槽的衬底，其中包括沟槽电容器，导电柱，套环电介质层和顶部电介质层。 具有侧壁上的间隔物的栅极结构设置在衬底上并与沟槽相邻。 在轴环电介质层和栅极结构之间的基板上形成开口。 接下来，去除顶部电介质层和套环电介质层的一部分以暴露导电柱的一部分。 绝缘层沉积在栅极结构和暴露的导电柱上，填充开口。 蚀刻绝缘层以暴露基板和导电柱的电容器侧区域的一部分。 通过选择性沉积形成透射带，电连接基板的电容器侧区域和导电柱。

公开(公告)号：US20070099125A1

公开(公告)日：2007-05-03

申请号：US11564238

申请日：2006-11-28

Applicant: Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

Inventor： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC: G03C5/00

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract translation: 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US20060228845A1

公开(公告)日：2006-10-12

申请号：US11101007

申请日：2005-04-06

Applicant: Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

Inventor： Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10888

Abstract: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.

公开(公告)号：US06919245B2

公开(公告)日：2005-07-19

申请号：US10972505

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract translation: 用于布置深沟槽和有源区域的动态随机存取存储器（DRAM）单元布局及其制造方法。 有源区域包括两个垂直晶体管，一个常见的位线触点和两个深沟槽。 第一垂直晶体管形成在第一深沟槽与第一栅极导电线部分重叠的区域上。 第二垂直晶体管形成在第二深沟槽与第二栅极导电线部分重叠的区域上。

公开(公告)号：US06534359B2

公开(公告)日：2003-03-18

申请号：US09854590

申请日：2001-05-15

Applicant: Kuen-Chy Heo ,  Jeng-Ping Lin

Inventor： Kuen-Chy Heo ,  Jeng-Ping Lin

IPC: H01L218242

CPC classification number: H01L27/10864 ,  H01L27/10876

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. Accordinng to this method, a semiconductor substrate is first provided. A pad layer is formed on the surface of the substrate. A deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is deposited to form a buried strap and an opening. A first insulating layer and a second masking layer are formed and fill the opening. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned. A second insulating layer is deposited and forms a Shallow Trench Isolation. A portion of the second masking layer is removed. The pad layer is removed to expose the substrate. A well is formed in the exposed substrate after forming a third insulating layer. The third insulating layer and the first insulating layer are then removed. The second masking layer is removed. A fourth insulating layer is deposited to form the gate oxide. Sequentially, a third and a fourth conductive layers are deposited to form the gate. Finally, the source/drain regions and the gate spacers are formed to complete the fabrication of the vertical transistor of a memory cell.

Abstract translation: 公开了一种制造存储器单元的垂直晶体管的方法。 根据该方法，首先提供半导体衬底。 衬底层形成在衬底的表面上。 在衬底中形成深沟槽。 在深沟槽中，形成沟槽电容器，然后在沟槽电容器上方的侧壁上形成环状氧化物层。 第一导电层形成在沟槽电容器的上方。 沉积第二导电层以形成掩埋带和开口。 形成第一绝缘层和第二掩模层并填充开口。 衬垫层，衬底，第二掩模层，第一绝缘层，环氧化物层和第一导电层被图案化。 沉积第二绝缘层并形成浅沟槽隔离。 去除第二掩蔽层的一部分。 去除衬垫层以露出衬底。 在形成第三绝缘层之后，在暴露的衬底中形成阱。 然后去除第三绝缘层和第一绝缘层。 去除第二掩蔽层。 沉积第四绝缘层以形成栅极氧化物。 顺序地，沉积第三和第四导电层以形成栅极。 最后，形成源极/漏极区域和栅极间隔物以完成存储器单元的垂直晶体管的制造。