公开(公告)号：US07202162B2

公开(公告)日：2007-04-10

申请号：US10420311

申请日：2003-04-22

Applicant: Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

Inventor： Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/28562

Abstract: A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.

Abstract translation: 已经开发了用于改善底层铜结构和上覆材料和结构之间的粘合性的方法。 该方法特征是在铜结构上形成氮化钽层，其中铜结构位于镶嵌型开口中。 为了获得最大的附着效益，通过在特定沉积条件下进行的原子沉积层程序形成氮化钽层。 底层铜结构和上覆材料（例如氮化硅蚀刻停止层）之间的粘附以及下层铜结构和上层金属互连结构之间的粘附性得到改善，原因在于沉积的原子层的存在 氮化钽层。

公开(公告)号：US07193327B2

公开(公告)日：2007-03-20

申请号：US11042396

申请日：2005-01-25

Applicant: Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

Abstract translation: 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

公开(公告)号：US20070035026A1

公开(公告)日：2007-02-15

申请号：US11203237

申请日：2005-08-15

Applicant: Yi-Nien Su ,  Jyu-Horng Shieh ,  Cheng-Lin Huang ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Yi-Nien Su ,  Jyu-Horng Shieh ,  Cheng-Lin Huang ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76847 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening in a semiconductor device with improved step coverage. The opening comprises a dielectric layer overlying a substrate, having at least one via opening to expose the substrate. The via opening comprises a step region in the upper portion of the via opening and a concave profile region with respect to the dielectric layer in the lower portion of the via opening. A semiconductor device with the opening is also disclosed.

Abstract translation: 半导体器件的开口，具有改进的台阶覆盖。 开口包括覆盖衬底的电介质层，具有至少一个通孔以暴露衬底。 通孔开口包括在通孔开口的上部中的台阶区域和相对于通孔开口下部的电介质层的凹形轮廓区域。 还公开了一种具有开口的半导体器件。

公开(公告)号：US20060163746A1

公开(公告)日：2006-07-27

申请号：US11042396

申请日：2005-01-25

Applicant: Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shing-Chyang Pan ,  Shau-Lin Shue ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Hsien-Ming Lee ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.

Abstract translation: 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。

公开(公告)号：US20060027925A1

公开(公告)日：2006-02-09

申请号：US11024916

申请日：2004-12-28

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC: H01L29/788

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract translation: 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

公开(公告)号：US06969675B2

公开(公告)日：2005-11-29

申请号：US10942355

申请日：2004-09-16

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层是通过沉积氮化钨底层，然后沉积原位SiH 4 / NH 3或SiH 4 H / 浸泡形成WSiN层，并沉积钨的最终顶层。 本发明用于在用于逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US20050245072A1

公开(公告)日：2005-11-03

申请号：US10833154

申请日：2004-04-28

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: H01L21/288 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract translation: 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US20050097769A1

公开(公告)日：2005-05-12

申请号：US10668291

申请日：2003-09-24

Applicant: Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC: H01L21/677 ,  F26B13/30

CPC classification number: H01L21/67781

Abstract: A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

Abstract translation: 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

公开(公告)号：US06878615B2

公开(公告)日：2005-04-12

申请号：US09863224

申请日：2001-05-24

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

Abstract translation: 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US06706629B1

公开(公告)日：2004-03-16

申请号：US10338120

申请日：2003-01-07

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Abstract translation: 提供了一种新的方法来产生包括铜的金属互连。 本发明的第一实施例提供了铜掺杂层的应用。 本发明的第二个实施例提供了在介质层中形成的开口的表面上沉积作为隔离膜的氮化硅层，然后从开口的底部去除氮化硅层，随后沉积 在该开口的表面上的铜掺杂合金种子层，然后在铜合金种子层上镀一层铜。