公开(公告)号：US20090184429A1

公开(公告)日：2009-07-23

申请号：US12354140

申请日：2009-01-15

申请人： Andreas Thies ,  Sirko Kramp ,  Helmut Schneider ,  Rainer Florian Schnabel

发明人： Andreas Thies ,  Sirko Kramp ,  Helmut Schneider ,  Rainer Florian Schnabel

IPC分类号： H01L23/522 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/105 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

摘要翻译： 集成电路包括第一导线和第二线以及与第一和第二导线接触的接触结构。 第一导电线被布置在第一金属化水平中，并且第二导电线被布置在布置在第一金属化层上方的第二金属化水平。 第二导线布置在接触结构的上方，相邻接触结构的间距等于相邻的第二导线的间距。 相邻接触结构之间的距离小于100nm。

公开(公告)号：US07542362B2

公开(公告)日：2009-06-02

申请号：US11872573

申请日：2007-10-15

申请人： Martin Versen ,  Helmut Schneider

发明人： Martin Versen ,  Helmut Schneider

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099

摘要： A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

摘要翻译： 一种用于访问存储器单元的逻辑内容的设备，所述存储单元包括用于存储与所述逻辑内容相关的电荷的单元容量，其中所述单元容量连接在具有位线容量的位线和参考电位之间， 该装置包括：具有小于所述位线容量的参考容量的参考节点; 以及用于在存储单元的读取或写入访问的情况下分别改变位线和参考节点的电位的电路，其中，利用第一电​​流进行位线的电位变化，并且改变 参考节点的电位用第二电流进行，其中第一电流大于第二电流。

公开(公告)号：US20090021996A1

公开(公告)日：2009-01-22

申请号：US12174295

申请日：2008-07-16

申请人： Martin Versen ,  Helmut Schneider

发明人： Martin Versen ,  Helmut Schneider

IPC分类号： G11C7/12 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C2029/1204

摘要： A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control circuit. The bit line control circuit is configured to write, in a bit line-selective manner, a weak value to a memory cell coupled to a bit line selected.

摘要翻译： 存储电路包括多个位线和可经由相应位线写入的多个存储单元。 存储电路还包括位线控制电路。 位线控制电路被配置为以位线选择性方式将一弱值写入耦合到所选位线的存储单元。

公开(公告)号：US07359271B2

公开(公告)日：2008-04-15

申请号：US11313650

申请日：2005-12-22

申请人： Helmut Schneider ,  Harald Streif

发明人： Helmut Schneider ,  Harald Streif

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C29/783 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits. A cyclical self-refresh operation is provided to refresh the WLs associated with subsets of the wordline driver circuits to reduce the overall GIDL current associated with the plurality of wordline driver circuits.

摘要翻译： 一种半导体集成电路器件和方法，用于减少与诸如半导体集成电路存储器件的半导体电子器件的电路相关联的栅极感应漏电流。 在待机模式期间，提供给多个电路的电压减小，以便减少与所述多个电路相关联的栅极感应泄漏（GIDL）电流。 在处于待机模式的时间间隔期间，提供给所述多个电路的子集的电压增加到与所述多个电路的所述子集相关联的刷新功能所需的电平，然后在所述刷新功能完成时减小 。 在该示例中，半导体存储器件，以这种方式操作的电路是字线驱动器电路。 提供循环自刷新操作以刷新与字线驱动器电路的子集相关联的WL，以减少与多个字线驱动器电路相关联的总体GIDL电流。

公开(公告)号：US20080007126A1

公开(公告)日：2008-01-10

申请号：US11750899

申请日：2007-05-18

申请人： Vladimir POPOV ,  Helmut Schneider

发明人： Vladimir POPOV ,  Helmut Schneider

IPC分类号： H02K1/12 ,  H02K37/00

CPC分类号： H02K1/145 ,  H02K37/14

摘要： A claw pole stator for a stepping motor having at least a first and a second claw pole plate, each of which has a yoke and pole claws, the first and the second claw pole plate having the same number of pole claws and pole gaps and being coaxially disposed with respect to one another, wherein the pole claws of the first claw pole plate engage in the pole gaps of the second claw pole plate, and having a toroid coil that is located between the first claw pole plate and the second claw pole plate and at least the pole claws of the first claw pole plate being divided into several sections that comprise a first section that is connected to the yoke and is substantially trapezoidal in shape and tapered, narrowing with increasing distance from the yoke and that comprise a second section that adjoins the first section and is substantially rectangular in shape.

摘要翻译： 一种用于步进电机的爪极定子，至少具有第一和第二爪极板，每个具有轭和杆爪，第一和第二爪极板具有相同数量的极爪和极间隙，并且是 其中，第一爪极板的极爪与第二爪极板的极间隙接合，并且具有位于第一爪极板和第二爪极板之间的环形线圈 并且至少所述第一爪极板的极爪被分成几个部分，所述多个部分包括连接到所述轭的大致梯形的第一部分，并且呈锥形，并且随着与所述轭的距离增加而变窄，并且包括第二部分 其邻接第一部分并且基本上是矩形的形状。

公开(公告)号：US07242125B2

公开(公告)日：2007-07-10

申请号：US11178460

申请日：2005-07-12

申请人： Helmut Schneider ,  Ulrich Kreiensen

发明人： Helmut Schneider ,  Ulrich Kreiensen

IPC分类号： H02K3/34 ,  H02K5/00 ,  H02K7/00

CPC分类号： H02K3/522 ,  H02K3/345 ,  H02K3/38 ,  H02K3/50

摘要： The invention relates to a device for the insulation of the stator slots of an electric machine that has a stator having a plurality of stator poles and stator slots located between the stator poles, comprising an insulating body that has moldings adapted to the shape of the stator slots and can be slid onto the stator in an axial direction, and a cover piece that can be connected to an end face of the insulating body, in order after the windings have been applied to the insulating body, to carry the windings (36) at the end face of the stator and to cover them.

公开(公告)号：US07009263B2

公开(公告)日：2006-03-07

申请号：US10830675

申请日：2004-04-23

申请人： Gerhard Enders ,  Bjoern Fischer ,  Helmut Schneider ,  Peter Voigt

发明人： Gerhard Enders ,  Bjoern Fischer ,  Helmut Schneider ,  Peter Voigt

IPC分类号： H01L29/76

CPC分类号： H01L29/0649 ,  H01L29/1033

摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

摘要翻译： 场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极， 漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域 和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响， 电极，布置在第一和第二窄宽度通道区域的上方。

公开(公告)号：US20050207251A1

公开(公告)日：2005-09-22

申请号：US11068491

申请日：2005-03-01

申请人： Helmut Schneider ,  Michael Sommer

发明人： Helmut Schneider ,  Michael Sommer

IPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G11C7/062

摘要： An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUX1, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.

摘要翻译： 集成半导体存储器包括具有用于驱动第一存储单元阵列的存储单元的第一子放大器的读出放大器和用于驱动第二存储单元阵列的存储单元的第二子放大器。 子放大器通过连续线连接到第一存储单元阵列的位线和第二存储单元阵列的位线。 可以通过在第一操作状态下应用单个控制信号（MUX1，MUXr）来读取和刷新存储器单元的信息并且在用于对位线进行预充电的第二操作状态下来操作子放大器。 由于将副放大器直接耦合到相应的存储单元阵列，所以避免了由于损耗导致的信号线的减少。

公开(公告)号：US20050052916A1

公开(公告)日：2005-03-10

申请号：US10878676

申请日：2004-06-29

申请人： Martin Brox ,  Helmut Schneider

发明人： Martin Brox ,  Helmut Schneider

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/40615 ,  G11C2211/4067

摘要： The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.

摘要翻译： 本发明涉及半导体存储器，特别涉及具有存储器子单元的DRAM，其中存储器子单元包括其中存储数据值的存储单元，并且适用于与分配有互补位线的位线连接， 分配给存储单元的预充电/均衡电路，预充电/均衡电路用于在存储单元的区域读出存储单元之前将位线和互补位线读取到相同的电压电平， 并且在读出存储器单元期间被关闭。 此外，半导体存储器具有与预充电/均衡电路连接的控制电路，用于接通和关断预充电/均衡电路。

公开(公告)号：US20050009147A1

公开(公告)日：2005-01-13

申请号：US10848279

申请日：2004-05-18

申请人： Wilfried Bauer ,  Robin Breckenridge ,  Francois Cardinaux ,  Frank Gombert ,  Hermann Gram ,  Paul Ramage ,  Helmut Schneider ,  Rudolf Waelchli ,  Rainer Albert ,  Ian Lewis

发明人： Wilfried Bauer ,  Robin Breckenridge ,  Francois Cardinaux ,  Frank Gombert ,  Hermann Gram ,  Paul Ramage ,  Helmut Schneider ,  Rudolf Waelchli ,  Rainer Albert ,  Ian Lewis

IPC分类号： C07K9/00 ,  A61K38/00 ,  A61K38/22 ,  A61K38/29 ,  A61P3/00 ,  A61P3/14 ,  A61P19/08 ,  A61P43/00 ,  C07K20060101 ,  C07K14/01 ,  C07K14/195 ,  C07K14/41 ,  C07K14/635 ,  C07K19/00 ,  C12N1/20 ,  C12N1/21 ,  C12N5/10 ,  C12N15/09 ,  C12N15/16 ,  C12N15/62 ,  C12P21/02 ,  C12R1/19 ,  C07H21/04

CPC分类号： C07K14/005 ,  A61K38/00 ,  C07K14/635 ,  C07K2319/00 ,  C07K2319/50 ,  C07K2319/75 ,  C12N2795/10222

摘要： PTH compounds having PTH-like activity and comprising at least one modification, said modification being either 1. at least one radical selected from a L- or D-α-amino acid, C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to the terminal amino group of the PTH compound, and/or at least one radical selected from C2-6alcoxycarbonyl and optionally substituted C1-8alkyl, C2-8alkenyl, C2-8alkynyl, aralkyl, aralkenyl or C3-6cycloalkyl-C1-4alkyl and attached to one or more side chain amino groups of the PTH compound, or 2. at least one α-amino acid unit in the positions 1 to 38 of a naturally occurring PTH sequence being replaced by a natural or unnatural amino acid unit optionally in protected form, whereby the α-amino acid units present in positions 1 and 2 at the amino terminus of the PTH sequence may be replaced by a pseudo-peptide, or a combination of such modifications, in free form or in salt form, have pharmacological activity, e.g. for preventing or treating all bone conditions which are associated with increased calcium depletion or resorption or in which calcium fixation in the bone is desirable.

摘要翻译： 具有PTH样活性并且包含至少一个修饰的PTH化合物，所述修饰是1.至少一个选自L-或D-α-氨基酸，C2-6羰基和任选取代的C 1-8烷基的基团，C 2-8烯基 ，C 2-8炔基，芳烷基，芳烯基或C 3-6环烷基-C 1-4烷基，并且连接到PTH化合物的末端氨基，和/或至少一个选自C 2-6烷氧基羰基和任选取代的C 1-8烷基基团，C 2-8烯基 ，C 2-8炔基，芳烷基，芳烯基或C 3-6环烷基-C 1-4烷基，并且连接到PTH化合物的一个或多个侧链氨基，或2个至少一个α-氨基酸单元的位置1至38 天然存在的PTH序列被任选以保护形式的天然或非天然氨基酸单元替代，由此存在于PTH序列的氨基末端的位置1和2中的α-氨基酸单元可被假肽替代，或 这些修改的组合，免费的 m或盐形式，具有药理活性，例如。 用于预防或治疗与增加的钙耗竭或吸收相关的所有骨骼状况或其中期望骨中的钙固定。