公开(公告)号：US06258627B1

公开(公告)日：2001-07-10

申请号：US09233388

申请日：1999-01-19

申请人： Joseph A. Benenati ,  William T. Chen ,  Lisa A. Fanti ,  Wayne J. Howell ,  John U. Knickerbocker

发明人： Joseph A. Benenati ,  William T. Chen ,  Lisa A. Fanti ,  Wayne J. Howell ,  John U. Knickerbocker

IPC分类号： H01L2144

CPC分类号： H01L24/28 ,  H01L21/563 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00

摘要： An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive. Preferably, the first solder is disposed within an interior of the apertures and the second solder is disposed within an exterior of the apertures such that the first solder is between a first portion and a second portion of the second solder. Upon reflow, the second solder is reflowed while the first solder remains solid.

摘要翻译： 用于最小化倒装芯片封装的热机械疲劳的装置和方法。 本发明的插入物优选包含有机聚合物如聚酰亚胺，其中包含插入其中的导电插塞孔，其中使用倒装芯片封装将芯片连接到电子模块中的基片。 选择插入器以在芯片和衬底之间提供适合于模块部件的热循环温度极限的热膨胀系数的最佳间隔。 插入器可以包括具有两个粘合剂外层的内芯，其可以包括不同的材料以促进在其模块内的各自界面处的粘附。 导电插头设置在插入件的孔内，包括第一和第二焊料或包括具有涂覆有导电粘合剂的顶表面和底表面的导电插塞。 优选地，第一焊料设置在孔的内部，并且第二焊料设置在孔的外部内，使得第一焊料位于第二焊料的第一部分和第二部分之间。 在回流时，第二焊料回流，而第一焊料保持固体。

公开(公告)号：US06559666B2

公开(公告)日：2003-05-06

申请号：US09875246

申请日：2001-06-06

申请人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

发明人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

IPC分类号： G01R3102

CPC分类号： G01R31/2886 ,  H01L2224/45144 ,  H01L2224/81385 ,  H01L2224/83101 ,  H05K3/321 ,  H01L2924/00

摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

摘要翻译： 一种用于测试和燃烧半导体电路的方法和装置。 该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。 此外，ECA可以沉积在C4凸点或锡盖铅基上。 该方法和装置的变化包括用ECA填充非导电插入件的通孔。 可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。 为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。 在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

公开(公告)号：US06426241B1

公开(公告)日：2002-07-30

申请号：US09439112

申请日：1999-11-12

申请人： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

发明人： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

IPC分类号： H01L2144

CPC分类号： H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H05K3/101 ,  H05K3/107 ,  H05K3/3421 ,  H05K2201/0305 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2203/128 ,  H01L2924/00

摘要： A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

摘要翻译： 提供了一种用于在基板中形成三维电路的方法，用于形成导电迹线和通孔触点。 在该方法中，首先提供由基本绝缘材料形成的基板，然后形成在基板的顶表面中的沟槽和孔，然后用导电材料（例如焊料）填充凹槽和孔。 该方法可以以低成本进行，以通过使用注射成型焊接技术或熔融焊料筛选技术来填充槽和孔来产生高质量的电路基板。 衬底中的凹槽和孔可以通过各种技术形成，例如化学蚀刻，物理加工和热冲压。

公开(公告)号：US06268739B1

公开(公告)日：2001-07-31

申请号：US09478678

申请日：2000-01-06

申请人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

发明人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

IPC分类号： G01R3102

CPC分类号： G01R31/2886 ,  H01L2224/45144 ,  H01L2224/81385 ,  H01L2224/83101 ,  H05K3/321 ,  H01L2924/00

摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

公开(公告)号：US5926029A

公开(公告)日：1999-07-20

申请号：US863268

申请日：1997-05-27

申请人： Thomas G. Ference ,  Wayne J. Howell

发明人： Thomas G. Ference ,  Wayne J. Howell

IPC分类号： G01R1/073 ,  G01R31/02 ,  G01R31/26

CPC分类号： G01R1/0735

摘要： This discloses a probe structure which does not rely on cantilevered wire and which has improved and controlled contact pressure between the probe tip contacts and the I/O pads on a semiconductor chip and which comprises a plurality of conductive contact electrodes, electrically coupled to respective leads, formed on a film stretched across a respective plurality of through holes established in a substrate. The through holes and the contact electrodes are aligned with one another and both positionally match selected I/O pads existing on a semiconductor chip to be probed. Also disclosed is a probe utilizing means connected to each one of the holes to control the pressure in the holes and between the probes and any contact on a device in contact with the probe.

摘要翻译： 这公开了一种探头结构，其不依赖于悬臂线，并且其具有改善和控制探针尖端触点与半导体芯片上的I / O焊盘之间的接触压力，并且包括多个导电接触电极，电耦合到各个引线 形成在延伸穿过建立在基板中的相应多个通孔的膜上。 通孔和接触电极彼此对准，并且两者位置匹配存在于待探测的半导体芯片上的所选择的I / O焊盘。 还公开了一种探针利用装置，其连接到每个孔中以控制孔中和探针之间的压力以及与探针接触的装置上的任何接触。