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    Method and device for semiconductor testing using electrically conductive adhesives
    1.
    发明授权
    Method and device for semiconductor testing using electrically conductive adhesives 失效
    使用导电胶粘剂进行半导体测试的方法和装置

    公开(公告)号：US06559666B2

    公开(公告)日：2003-05-06

    申请号：US09875246

    申请日：2001-06-06

    申请人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

    发明人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

    IPC分类号： G01R3102

    CPC分类号： G01R31/2886 ,  H01L2224/45144 ,  H01L2224/81385 ,  H01L2224/83101 ,  H05K3/321 ,  H01L2924/00

    摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

    摘要翻译： 一种用于测试和燃烧半导体电路的方法和装置。 该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。 此外，ECA可以沉积在C4凸点或锡盖铅基上。 该方法和装置的变化包括用ECA填充非导电插入件的通孔。 可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。 为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。 在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

    Method of fabricating a flex laminate package
    4.
    发明授权
    Method of fabricating a flex laminate package 失效
    柔性层压包装的制造方法

    公开(公告)号：US5620782A

    公开(公告)日：1997-04-15

    申请号：US459929

    申请日：1995-06-02

    申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

    发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

    IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  B32B9/00

    CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

    摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the per fluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the per fluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

    摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过低熔点粘合剂来实现的，该低熔点粘合剂与要层压的区域中的子组件之间的每个碳氟化合物聚合物化学相容（可粘合），以及任选的与化学不相容的高熔点掩模 不能粘合）在不想层压的区域中的子组件之间的每个碳氟聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

    Semiconductor testing using electrically conductive adhesives
    8.
    发明授权
    Semiconductor testing using electrically conductive adhesives 失效
    使用导电胶的半导体测试

    公开(公告)号：US06288559B1

    公开(公告)日：2001-09-11

    申请号：US09050820

    申请日：1998-03-30

    申请人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

    发明人： William E. Bernier ,  Michael A. Gaynes ,  Wayne J. Howell ,  Mark V. Pierson ,  Ajit K. Trivedi ,  Charles G. Woychik

    IPC分类号： G01R3102

    CPC分类号： G01R31/2886 ,  H01L2224/45144 ,  H01L2224/81385 ,  H01L2224/83101 ,  H05K3/321 ,  H01L2924/00

    摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

    摘要翻译： 一种用于测试和燃烧半导体电路的方法和装置。 该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。 此外，ECA可以沉积在C4凸点或锡盖铅基上。 该方法和装置的变化包括用ECA填充非导电插入件的通孔。 可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。 为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。 在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

    Method for filling plated through holes
    9.
    发明授权
    Method for filling plated through holes 失效
    填充电镀通孔的方法

    公开(公告)号：US5435480A

    公开(公告)日：1995-07-25

    申请号：US172064

    申请日：1993-12-23

    申请人： Paul J. Hart ,  Kishor V. Desai ,  Edward Vytlacil ,  Ajit K. Trivedi

    发明人： Paul J. Hart ,  Kishor V. Desai ,  Edward Vytlacil ,  Ajit K. Trivedi

    IPC分类号： H05K3/34 ,  H05K3/40

    CPC分类号： H05K3/3484 ,  H05K3/3478 ,  H05K2201/09572 ,  H05K2203/0191 ,  H05K2203/041 ,  H05K2203/0425 ,  H05K2203/043 ,  H05K2203/0568 ,  Y10T29/49126

    摘要： Plated thru holes in a printed circuit card or board are filled with solder to provide as void free as possible solder fill. According to one method, an adhesive film is provided on the bottom side of a circuit card or board containing plated thru holes. A plurality of solder balls are then provided within at least one thru hole of the card or board. The total volume of the solder balls is greater than the volume of the plated thru hole. The solder balls are reflowed to thereby fill the plated thru hole with solder and provide solder on top of the thru hole.According to another method, a solder ball is provided above and in contact with a plated thru hole. The volume of the solder ball is greater than the volume of the plated thru hole. The solder ball is reflowed to thereby fill the plated thru hole with solder, and to provide solder both above and below the plated thru hole.

    摘要翻译： 印刷电路板或电路板上的通孔穿过焊料，以提供尽可能无铅的焊料填充。 根据一种方法，在包含电镀通孔的电路卡或板的底侧上设置粘合膜。 然后在卡或板的至少一个通孔内提供多个焊球。 焊球的总体积大于电镀通孔的体积。 焊球回流，由此用焊料填充电镀通孔，并在通孔的顶部提供焊料。 根据另一种方法，在电镀通孔上方并与电镀通孔相接触地设置焊球。 焊球的体积大于电镀通孔的体积。 将焊球回流，由此用焊料填充电镀通孔，并在电镀通孔上方和下方提供焊料。

    Flex laminate package for a parallel processor
    10.
    发明授权
    Flex laminate package for a parallel processor 失效
    用于并行处理器的Flex层压包装

    公开(公告)号：US5384690A

    公开(公告)日：1995-01-24

    申请号：US97544

    申请日：1993-07-27

    申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

    发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

    IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H01R23/68

    CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

    摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

    摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。