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133 条记录 (耗时 0.027 秒)

    Apparatus for drying substrate and method thereof
    35.
    发明申请
    Apparatus for drying substrate and method thereof 失效
    干燥基材的设备及其方法

    公开(公告)号：US20060042722A1

    公开(公告)日：2006-03-02

    申请号：US11158912

    申请日：2005-06-22

    申请人： Sang-Yong Kim ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Woo-Gwan Shim

    发明人： Sang-Yong Kim ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Woo-Gwan Shim

    IPC分类号： B65B1/04

    CPC分类号： H01L21/67051 ,  H01L21/67034

    摘要： An apparatus for drying a substrate using the Marangoni effect is disclosed. The apparatus includes a rotatable supporting portion on which a substrate is placed. A first nozzle for supplying de-ionized water and a second nozzle for supplying isopropyl alcohol vapor are provided on the supporting portion. When the isopropyl alcohol vapor is supplied to the center of the substrate at the initial stage, the amount of alcohol that reaches the substrate is controlled by a controlling portion such that the amount of the second liquid gradually increases.

    摘要翻译： 公开了一种使用Marangoni效应对基板进行干燥的装置。 该装置包括可旋转的支撑部分，放置基板。 用于提供去离子水的第一喷嘴和用于提供异丙醇蒸气的第二喷嘴设置在支撑部分上。 当在初始阶段将异丙醇蒸汽供应到基材的中心时，通过控制部分控制到达基板的醇的量，使得第二液体的量逐渐增加。

    Methods for cleaning a semiconductor substrate having a recess channel region
    36.
    发明申请
    Methods for cleaning a semiconductor substrate having a recess channel region 失效
    用于清洁具有凹槽通道区域的半导体衬底的方法

    公开(公告)号：US20060030117A1

    公开(公告)日：2006-02-09

    申请号：US11194794

    申请日：2005-08-01

    申请人： Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Dong-Gyun Han

    发明人： Hyung-Ho Ko ,  Chang-Ki Hong ,  Sang-Jun Choi ,  Dong-Gyun Han

    IPC分类号： H01L21/76 ,  H01L21/302

    CPC分类号： H01L21/30604 ,  H01L21/0206 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  Y10S438/906

    摘要： A method for cleaning a semiconductor substrate forming device isolation layers in a predetermined region of a semiconductor substrate to define active regions; etching predetermined areas of the active regions to form a recess channel region and such that sidewalls of the device isolation layers are exposed; and selectively etching a surface of the recess channel region using a predetermined cleaning solution to clean the semiconductor substrate where the recess channel region has been formed.

    摘要翻译： 一种用于清洁在半导体衬底的预定区域中形成器件隔离层的半导体衬底以限定有源区域的方法; 蚀刻有源区域的预定区域以形成凹陷沟道区域，并且使得器件隔离层的侧壁被暴露; 并且使用预定的清洗溶液选择性地蚀刻凹槽通道区域的表面，以清洁已经形成凹槽通道区域的半导体衬底。

    Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness
    39.
    发明授权
    Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness 有权
    制造具有包括不同厚度的两个以上部分的隧道绝缘层的非易失性存储器件的方法

    公开(公告)号：US06709920B2

    公开(公告)日：2004-03-23

    申请号：US09902243

    申请日：2001-07-10

    申请人： Jae-Phil Boo ,  Soo-Young Tak ,  Kwang-Bok Kim ,  Kyung-Hyun Kim ,  Chang-Ki Hong

    发明人： Jae-Phil Boo ,  Soo-Young Tak ,  Kwang-Bok Kim ,  Kyung-Hyun Kim ,  Chang-Ki Hong

    IPC分类号： H01L218242

    CPC分类号： H01L27/11526 ,  H01L27/11531

    摘要： A method of fabricating a non-volatile memory device, which has a tunnel insulating layer consisting of two or more portions of different thickness, cell transistors, and auxiliary transistors for applying external voltage and for interfacing with peripheral circuits is described. According to the method, the tunnel insulating layer, a conductive layer, and a first insulating layer are sequentially deposited over a semiconductor substrate. The resultant structure is selectively etched to a given depth to form trenches. A second insulating layer is deposited over the substrate including the trenches, and the second insulating layer is selectively removed so as to form element isolation regions consisting of the trenches filled with the second insulating layer. The first insulating layer is selectively removed, and the second insulating layer is selectively removed by a CMP process to expose the conductive layer. The conductive layer is used as the stopping layer during the CMP process.

    摘要翻译： 描述了制造具有由不同厚度的两个或更多个部分组成的隧道绝缘层的单元晶体管和用于施加外部电压并与外围电路接口的辅助晶体管的非易失性存储器件的制造方法。 根据该方法，隧道绝缘层，导电层和第一绝缘层依次沉积在半导体衬底上。 将所得结构选择性地蚀刻到给定的深度以形成沟槽。 在包括沟槽的衬底上沉积第二绝缘层，并且选择性地去除第二绝缘层，以便形成由填充有第二绝缘层的沟槽组成的元件隔离区域。 选择性地去除第一绝缘层，并且通过CMP工艺选择性地去除第二绝缘层以暴露导电层。 在CMP工艺期间，导电层用作停止层。

    Methods of forming trench isolation structures by etching back electrically insulating layers using etching masks
    40.
    发明授权
    Methods of forming trench isolation structures by etching back electrically insulating layers using etching masks 有权
    通过使用蚀刻掩模蚀刻电绝缘层来形成沟槽隔离结构的方法

    公开(公告)号：US06169002A

    公开(公告)日：2001-01-02

    申请号：US09216192

    申请日：1998-12-18

    申请人： Chang-Ki Hong

    发明人： Chang-Ki Hong

    IPC分类号： H01L21336

    CPC分类号： H01L21/76224

    摘要： A trench is formed in the integrated circuit substrate via a mask and filled with an electrically insulating layer. The electrically insulating layer is etched back using the mask. After etching the electrically insulating layer the mask is removed. Etching the electrically insulating layer using the mask avoids the protrusion of the electrically insulating layer from the semiconductor substrate associated with the prior art and thereby may reduce the formation of grooves in the electrically insulating layer and improve the reliability of the electrically insulating layer.

    摘要翻译： 通过掩模在集成电路基板中形成沟槽并填充有电绝缘层。 使用掩模将电绝缘层回蚀刻。 在蚀刻电绝缘层之后，去除掩模。 使用掩模蚀刻电绝缘层避免了电绝缘层与现有技术相关的半导体衬底的突起，从而可以减少电绝缘层中凹槽的形成并提高电绝缘层的可靠性。