公开(公告)号：US08004893B2

公开(公告)日：2011-08-23

申请号：US12492209

申请日：2009-06-26

申请人： Jae-Sung Sim ,  Jung-Dal Choi

发明人： Jae-Sung Sim ,  Jung-Dal Choi

IPC分类号： G11C16/04

CPC分类号： H01L27/11551 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

摘要： Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

摘要翻译： 非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。 该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串还在其中设置有串联电连接的第二多个串选择晶体管。 第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。 根据本发明的这些实施例，第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠 晶体管。 第一串选择插头被配置为将第一增强型晶体管的栅极电连接到第二多个耗尽型晶体管之一的栅电极。 类似地，第二串选择插头被配置为将第二增强型晶体管的栅电极电连接到第一多个耗尽型晶体管之一的栅电极。

公开(公告)号：US07888219B2

公开(公告)日：2011-02-15

申请号：US12766272

申请日：2010-04-23

申请人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

发明人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

摘要翻译： 形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。 然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。 可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。 可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。

公开(公告)号：US07884425B2

公开(公告)日：2011-02-08

申请号：US12257939

申请日：2008-10-24

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.

摘要翻译： 在一个实施例中，半导体存储器件包括具有第一和第二有源区的衬底。 第一有源区包括第一源区和漏区，第二有源区包括第二源区和漏区。 第一层间电介质位于衬底上。 第一导电结构延伸穿过第一层间电介质。 第一位线位于第一层间电介质上。 第二层间电介质在第一层间电介质上。 接触孔延伸穿过第二和第一层间电介质。 该装置包括接触孔内的第二导电结构并且延伸穿过第一和第二层间电介质。 第二位线位于第二层间电介质上。 第二层间电介质的底部处的接触孔的宽度小于或基本上等于第二层间电介质顶部的宽度。

公开(公告)号：US07881114B2

公开(公告)日：2011-02-01

申请号：US12340250

申请日：2008-12-19

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

公开(公告)号：US07864582B2

公开(公告)日：2011-01-04

申请号：US12191434

申请日：2008-08-14

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

公开(公告)号：US07863676B2

公开(公告)日：2011-01-04

申请号：US11709814

申请日：2007-02-23

申请人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

发明人： Sang-Hun Jeon ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Won-Seok Jung

IPC分类号： H01L29/66

CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region.

摘要翻译： 半导体器件包括在半导体衬底中的器件隔离层，由器件隔离层限定的有源区，包括主表面的有源区和包括低于主表面的底表面的凹陷区，以及栅电极 形成在所述凹部区域上，其中，所述器件隔离层的与所述凹部区域相邻的顶面低于所述凹部区域的底面。

公开(公告)号：US07723776B2

公开(公告)日：2010-05-25

申请号：US11376371

申请日：2006-03-15

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

公开(公告)号：US20100065894A1

公开(公告)日：2010-03-18

申请号：US12622863

申请日：2009-11-20

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Uk-Jin Roh

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Uk-Jin Roh

IPC分类号： H01L27/105 ,  H01L29/772 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/792

摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

摘要翻译： 半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。 源/漏区限定在栅电极两侧的有源区中。 源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。 另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。 源极/漏极区域中的至少一个是场效应源极/漏极区域。 因此，在设备中减少或消除短的通道效应。

公开(公告)号：US20090310425A1

公开(公告)日：2009-12-17

申请号：US12471975

申请日：2009-05-26

申请人： Jae-Sung Sim ,  Jung-Dal Choi

发明人： Jae-Sung Sim ,  Jung-Dal Choi

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0408 ,  G11C16/14 ,  G11C16/26 ,  H01L21/823481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/7881

摘要： In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

摘要翻译： 在半导体器件和形成这种器件的方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 在基板上设置多个层间电介质层。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间介电层之间。 半导体材料的垂直沟道沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案，每个栅极图案和垂直沟道之间的栅极绝缘层将栅极图案与垂直沟道绝缘，垂直沟道 在包括半导体区域的接触区域处与衬底接触。

公开(公告)号：US20090230451A1

公开(公告)日：2009-09-17

申请号：US12382385

申请日：2009-03-16

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1083

摘要： A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

摘要翻译： 半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线 其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。