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    Semiconductor memory device to hold 5-bits of data per memory cell
    31.
    发明授权
    Semiconductor memory device to hold 5-bits of data per memory cell 有权

    公开(公告)号：US11361820B2

    公开(公告)日：2022-06-14

    申请号：US17143530

    申请日：2021-01-07

    Applicant: KIOXIA CORPORATION

    Inventor： Tomonori Takahashi ,  Masanobu Shirakawa ,  Osamu Torii ,  Marie Takada

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

    Memory system
    32.
    发明授权
    Memory system 有权

    公开(公告)号：US11334432B2

    公开(公告)日：2022-05-17

    申请号：US17092054

    申请日：2020-11-06

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Marie Takada

    IPC: G06F11/00 ,  G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

    Memory system
    33.
    发明授权
    Memory system 有权

    公开(公告)号：US11322210B2

    公开(公告)日：2022-05-03

    申请号：US17005273

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Marie Takada ,  Masanobu Shirakawa

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/14

    Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.

    Memory system
    36.
    发明授权
    Memory system 有权

    公开(公告)号：US12073890B2

    公开(公告)日：2024-08-27

    申请号：US18174916

    申请日：2023-02-27

    Applicant: KIOXIA CORPORATION

    Inventor： Masanobu Shirakawa ,  Tsukasa Tokutomi ,  Marie Takada

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

    Memory device
    40.
    发明授权
    Memory device 有权

    公开(公告)号：US11551756B2

    公开(公告)日：2023-01-10

    申请号：US17188046

    申请日：2021-03-01

    Applicant: Kioxia Corporation

    Inventor： Marie Takada ,  Masanobu Shirakawa

    IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56

    Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

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