公开(公告)号：US09653553B2

公开(公告)日：2017-05-16

申请号：US15055707

申请日：2016-02-29

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Johji Nishio ,  Kazuto Takao

IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L29/04 ,  H01L29/34 ,  C30B29/36 ,  H01L29/32 ,  H01L29/868 ,  H01L21/02

CPC分类号： H01L29/1608 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L29/045 ,  H01L29/32 ,  H01L29/34 ,  H01L29/36 ,  H01L29/7393 ,  H01L29/868

摘要： A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a direction plus or minus 5° from a {0001} face at an off angle of 0° to 10°. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm−2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5° and has a width of 30 μm or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 μm or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 μm or less.

公开(公告)号：US09559172B2

公开(公告)日：2017-01-31

申请号：US14205914

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Takashi Shinohe ,  Johji Nishio ,  Chiharu Ota

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/868 ,  H01L29/10 ,  H01L29/167 ,  H01L21/04 ,  H01L29/49

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/49 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/868

摘要： A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3.

摘要翻译： 实施例的半导体器件包括含有p型杂质和n型杂质的p型SiC杂质区。 当p型杂质是元素A，n型杂质是元素D时，元素A和元素D形成Al（铝），Ga（镓）或In（铟）和N（ 氮）和/或B（硼）和P（磷）的组合。 元素D的浓度与上述组合中的元素A的浓度的比例高于0.33但低于0.995，构成上述组合的一部分的元素A的浓度不低于1×1018cm -3且不高于1×1022cm-3。

公开(公告)号：US09484415B2

公开(公告)日：2016-11-01

申请号：US14468488

申请日：2014-08-26

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Kazuto Takao ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L29/16 ,  H01L29/36 ,  H01L21/02 ,  H01L29/861

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/02664 ,  H01L29/36 ,  H01L29/861

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.

摘要翻译： 根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域和第三半导体区域。 第一半导体区域包括碳化硅。 第一半导体区域的导电类型是第一导电类型。 第二半导体区域包括碳化硅。 第二半导体区域的导电类型是第二导电类型。 第三半导体区域包括碳化硅。 第三半导体的导电类型是第二导电类型。 第三半导体区域设置在第一半导体区域和第二半导体区域之间。 从连接第一半导体区域和第二半导体区域的方向观察，第二半导体区域和第三半导体区域的重叠区域的面积小于第一半导体区域和第二半导体区域的重叠区域的面积 地区。

公开(公告)号：US09318324B2

公开(公告)日：2016-04-19

申请号：US14656937

申请日：2015-03-13

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Chiharu Ota ,  Ryosuke Iijima ,  Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L21/02529 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/26513 ,  H01L29/1608

摘要： A manufacturing method of an SiC epitaxial substrate of an embodiment includes performing a first and a second process alternately to form an n type SiC layer, the first process forming a first SiC layer with an epitaxial growth process by using a first source gas containing an n type impurity, and the second process forming a second SiC layer with an epitaxial growth process by using a second source gas containing the n type impurity, the second source gas having a higher atomic ratio between C (carbon) and Si (silicon) (C/Si) than that of the first source gas, a thickness of the second SiC layer being smaller than a thickness of the first SiC layer.

摘要翻译： 实施例的SiC外延衬底的制造方法包括交替地执行第一和第二工艺以形成n型SiC层，所述第一工艺通过使用包含n型SiC的第一源气体，通过外延生长工艺形成第一SiC层 并且通过使用包含n型杂质的第二源气体，通过外延生长工艺形成第二SiC层的第二工艺，第二源气体在C（碳）和Si（硅）（C）之间具有较高的原子比 / Si），第二SiC层的厚度小于第一SiC层的厚度。

公开(公告)号：US09281365B2

公开(公告)日：2016-03-08

申请号：US14463846

申请日：2014-08-20

申请人： Kabushiki Kaisha Toshiba

发明人： Ryosuke Iljima ,  Kazuto Takao ,  Chiharu Ota ,  Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/049 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a first insulating section, and a second insulating section. The first semiconductor region includes silicon carbide, is of a first conductivity type and includes first and second parts. The second semiconductor region includes silicon carbide, is of a second conductivity type and is provided on the second part. The third semiconductor region includes silicon carbide, is of the first conductivity type and is provided on the second semiconductor region. The first electrode is provided on the first part and the third semiconductor region. The first insulating section is provided on the third semiconductor region and juxtaposed with the first electrode. The second insulating section is provided between the first electrode and the first part and between the first electrode and the first insulating section.

摘要翻译： 根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第一电极，第一绝缘部分和第二绝缘部分。 第一半导体区域包括碳化硅，是第一导电类型，并且包括第一和第二部分。 第二半导体区域包括碳化硅，其具有第二导电类型并且设置在第二部分上。 第三半导体区域包括碳化硅，其具有第一导电类型并且设置在第二半导体区域上。 第一电极设置在第一部分和第三半导体区域上。 第一绝缘部分设置在第三半导体区域上并且与第一电极并置。 第二绝缘部设置在第一电极和第一部分之间以及第一电极和第一绝缘部之间。

公开(公告)号：US09184229B2

公开(公告)日：2015-11-10

申请号：US13790282

申请日：2013-03-08

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Johji Nishio ,  Kazuto Takao ,  Takashi Shinohe

IPC分类号： H01L29/792 ,  H01L29/15 ,  H01L29/06 ,  H01L21/02 ,  H01L29/872 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/16

CPC分类号： H01L29/0615 ,  H01L21/0257 ,  H01L29/0638 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8613 ,  H01L29/872

摘要： According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region.

摘要翻译： 根据一个实施例，半导体器件包括：第一导电类型的第一半导体区域; 设置在所述第一半导体区域上的第二半导体区域，所述第二半导体区域的杂质浓度低于所述第一半导体区域的杂质浓度; 设置在第二半导体区域上的第二导电类型的第三半导体区域; 以及设置在第三半导体区域或第三半导体区域的一部分中的第四半导体区域。 第四半导体区域的晶格应变大于第三半导体区域的晶格应变。

公开(公告)号：US09171908B2

公开(公告)日：2015-10-27

申请号：US14205964

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Tatsuo Shimizu ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L29/167 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/808 ,  H01L29/868

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/046 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3, an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

摘要翻译： 实施方式的半导体装置具有：具有第一面和第二面的n型SiC衬底，含有p型杂质和n型杂质，p型杂质为元素A，n型杂质 作为元素D，元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（ 磷），组合物中元素A浓度与元素D浓度的比例高于0.40但小于0.95时，形成组合的元素D的浓度不低于 1×1018cm-3且不高于1×1022cm-3，形成在第一面上的SiC层，形成在第一表面侧上的第一电极和形成在第二面上的第二电极。

公开(公告)号：US09012923B2

公开(公告)日：2015-04-21

申请号：US14448345

申请日：2014-07-31

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Ryosuke Iijima ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L29/36 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78

CPC分类号： H01L29/36 ,  H01L21/046 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

摘要翻译： 实施例的半导体器件包括：n型第一SiC外延层; 在包含p型杂质和n型杂质的第一SiC外延层上的p型第二SiC外延层，p型杂质为元素A，n型杂质为元素D，元素A 并且形成Al，Ga或In和N的组合的元素D和/或B和P的组合，元素D与元素A的浓度比率高于0.33但低于1.0; 所述第二SiC外延层的表面的表面区域含有比所述第二SiC外延层低的浓度的所述元素A，所述比率高于所述第二SiC外延层中的比率; n型第一和第二SiC区域; 栅极绝缘膜; 栅电极; 第一电极; 和第二电极。

公开(公告)号：US20140284619A1

公开(公告)日：2014-09-25

申请号：US14205792

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Johji NISHIO ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/16

CPC分类号： H01L29/1608 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7827

摘要： An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

摘要翻译： 实施方案的SiC外延晶片包括SiC衬底和形成在SiC衬底上并包含p型杂质和n型杂质的p型第一SiC外延层。 元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（磷）的组合，当p 型杂质是元素A，n型杂质是元素D.组合（D）中元素D的浓度与元素A的浓度之比高于0.33但低于1.0。