利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

201 条记录 (耗时 0.038 秒)

    Nonvolatile semiconductor memory device
    34.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07224612B2

    公开(公告)日：2007-05-29

    申请号：US11194799

    申请日：2005-08-02

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    摘要翻译： NAND单元单元包括串联连接的多个存储单元。 对所有存储单元进行擦除操作。 然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并将11V施加到控制栅极 的剩余存储单元。 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Nonvolatile semiconductor memory
    35.
    发明申请
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US20060215458A1

    公开(公告)日：2006-09-28

    申请号：US11417248

    申请日：2006-05-04

    申请人： Ken Takeuchi

    发明人： Ken Takeuchi

    IPC分类号： G11C11/34

    CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483

    摘要： A system includes a nonvolatile semiconductor memory and an electronic device which includes the nonvolatile semiconductor memory. The nonvolatile semiconductor memory selects a first operation mode while the nonvolatile semiconductor memory is connected to a first capacitor having a first capacity, and the nonvolatile semiconductor memory selects a second operation mode while the nonvolatile semiconductor memory is connected to a second capacitor having a second capacity higher than a first capacity. The nonvolatile semiconductor memory operates in the selected one of the first and second operation modes. The first operation mode is a mode in which a peak of current consumption takes a first value, and a second operation mode is a mode in which a peak of current consumption takes a second value lower than the first value.

    摘要翻译： 一种系统包括非易失性半导体存储器和包括非易失性半导体存储器的电子器件。 非易失性半导体存储器选择第一操作模式，同时将非易失性半导体存储器连接到具有第一容量的第一电容器，并且非易失性半导体存储器选择第二操作模式，而非易失性半导体存储器连接到具有第二容量的第二电容器 高于第一容量。 非易失性半导体存储器以所选择的第一和第二操作模式操作。 第一操作模式是电流消耗的峰值取第一值，第二操作模式是电流消耗的峰值低于第一值的第二值的模式。

    Level shifter circuit and semiconductor memory device using same
    36.
    发明申请
    Level shifter circuit and semiconductor memory device using same 失效
    电平移位器电路和使用其的半导体存储器件

    公开(公告)号：US20060186942A1

    公开(公告)日：2006-08-24

    申请号：US11330143

    申请日：2006-01-12

    申请人： Takuya Futatsuyama ,  Ken Takeuchi

    发明人： Takuya Futatsuyama ,  Ken Takeuchi

    IPC分类号： H03L5/00

    CPC分类号： G11C16/08 ,  G11C16/0483 ,  H03K19/01855

    摘要： A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

    摘要翻译： 电平移位器电路包括具有第一导电率的第一输出MIS晶体管和具有第二阈值电压的第二导电类型的第二输出MIS晶体管。 前者具有第一阈值电压，其中输出电压被正向反馈到栅极端子，并且将电源电压施加到第一端子以在第二端子处产生第一电压。 在后者中，第一电压被施加到第一端子，并且第二电压被施加到栅极端子以控制导通以在第二端子处产生输出电压。 第一和第二充电型MIS晶体管和放电MIS晶体管连接在第二输出MIS晶体管的第一端子和栅极端子之间，以对第二输出MIS晶体管的栅极端子的电位进行充电或放电。

    Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
    37.
    发明申请
    Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
    半导体存储器件能够实现具有高操作可靠性和高产量的芯片

    公开(公告)号：US20060120130A1

    公开(公告)日：2006-06-08

    申请号：US11330352

    申请日：2006-01-12

    申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

    发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

    摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

    Non-volatile semiconductor memory
    40.
    发明授权
    Non-volatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US06937510B2

    公开(公告)日：2005-08-30

    申请号：US09800913

    申请日：2001-03-08

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列并彼此传送数据的第一锁存器和第二锁存器。 一个控制器控制重新编程和检索电路的数据重新编程操作和数据检索操作从存储单元阵列。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器在存储单元之一中存储两位四电平数据来执行二位四电平数据的高位和低位的重新编程和检索 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。