公开(公告)号：US5973706A

公开(公告)日：1999-10-26

申请号：US452349

申请日：1995-05-26

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F3/14 ,  G06T11/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  H04N5/262 ,  H04N5/265 ,  H04N5/278 ,  H04N9/64 ,  G09G5/00

CPC classification number: H04N9/641 ,  G09G5/14 ,  G09G5/366 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N21/4143 ,  H04N5/44 ,  H04N5/44504 ,  H04N5/44591 ,  H04N5/45 ,  G09G2340/045 ,  G09G2340/125 ,  G09G2360/126 ,  G09G5/026 ,  G09G5/393 ,  H04N5/4401

Abstract: A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.

Abstract translation: 一种包括微处理器，耦合到微处理器的总线，耦合到总线的视频存储器和显示装置的计算机系统。 还提供一个写入控制器，其耦合到总线，并且通过向视频存储器提供写入地址来控制将图像信号写入视频存储器。 写入控制器根据由微处理器设置的多个写入地址参数来改变写入地址的范围，使得要写入图像信号的视频存储器的存储器区域根据 写地址。 此外，由要写入视频存储器的图像信号表示的图像的尺寸改变。 还提供读控制器并且耦合到总线，用于通过与写入到视频存储器异步地向视频存储器提供读地址，并且与提供的同步信号同步地控制从视频存储器读出图像信号 与从视频存储器读出的图像信号一起到显示装置。

公开(公告)号：US5793439A

公开(公告)日：1998-08-11

申请号：US803227

申请日：1997-02-20

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G09G1/16 ,  G09G3/20 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  H04N5/44 ,  H04N5/445 ,  H04N5/45 ,  H04N9/64 ,  H04N9/74

CPC classification number: G09G1/167 ,  G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  H04N21/4143 ,  H04N5/44 ,  H04N5/44504 ,  H04N5/45 ,  H04N9/641 ,  G09G2340/0435 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2360/126 ,  G09G5/001 ,  G09G5/008 ,  G09G5/363 ,  G09G5/393 ,  H04N5/4401

Abstract: An image control device for use in a computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.

公开(公告)号：US5444497A

公开(公告)日：1995-08-22

申请号：US80501

申请日：1993-06-24

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F13/28 ,  G06T1/60 ,  G09G5/02 ,  G09G5/393

CPC classification number: G06F13/28 ,  G09G5/022 ,  G09G5/393 ,  H04N19/00 ,  G09G2340/12

Abstract: A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.

Abstract translation: 乘法器7将存储在加法地址存储器3中的加法地址乘以垂直计数器单元4的垂直计数输出。第一加法器8将乘法器7的乘积加到存储在偏移地址存储器2中的偏移地址。 第二加法器9将第一加法器8中的和加到水平计数器单元5中的水平计数。第三加法器10将第二加法器9中的和相加于存储在三个区域中的RGB颜色分量的每个区域起始地址。 开始地址存储单元6R，6G和6B。 来自第三加法器10的输出AD3成为DMA传输中的访问地址。 因此DMA传送中的访问地址通过DMA控制器34中的简单算术运算来计算，从而实现高速DMA传输。

公开(公告)号：US4975662A

公开(公告)日：1990-12-04

申请号：US420557

申请日：1989-10-18

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H03K3/03 ,  H03K3/354

CPC classification number: H03K3/03 ,  H03K3/354

Abstract: A voltage controlled oscillator (VCO) circuit includes a current mirror circuit section and oscillator circuit section to provide an oscillation frequency based on the output current of the current mirror circuit section. To vary the oscillation over a wide range, a fixed reference voltage circuit is connected to the current mirror circuit, and either a source follower circuit made of a MOSFET or a FET or an emitter follower circuit made of a bipolar transistor is included is also connected to the current mirror circuit to selectively varying the output current of the current mirror circuit section upon application of a control voltage applied to the follower circuit. Thus, the follower circuit is controlled by a control voltage while the output current of the current mirror circuit varies depending on the magnitude of the control voltage, and, in turn, the oscillating frequency of the oscillator circuit section varies over a wide frequency range, e.g., in excess of 100 dB, in accordance with the output current.

Abstract translation: 压控振荡器（VCO）电路包括电流镜电路部分和振荡器电路部分，以基于电流镜电路部分的输出电流提供振荡频率。 为了在宽范围内改变振荡，固定参考电压电路连接到电流镜电路，并且包括由MOSFET或FET制成的源极跟随器电路或由双极晶体管制成的射极跟随器电路也被连接 连接到电流镜电路，以在施加施加到跟随器电路的控制电压时选择性地改变电流镜电路部分的输出电流。 因此，跟随器电路由控制电压控制，而电流镜电路的输出电流根据控制电压的大小而变化，并且振荡器电路部分的振荡频率又在较宽的频率范围内变化， 例如，超过100dB，根据输出电流。

公开(公告)号：US08590386B2

公开(公告)日：2013-11-26

申请号：US13081730

申请日：2011-04-07

Applicant: Kesatoshi Takeuchi ,  Yojiro Okakura

Inventor： Kesatoshi Takeuchi ,  Yojiro Okakura

IPC: G01L9/10

CPC classification number: G01L1/14 ,  G01R33/072

Abstract: A pressure detection device includes a buffer member and a sensor assembly. The buffer member is deformable by a pressure change, and includes a plurality of magnets in an evenly dispersed arrangement. The sensor assembly includes at least one magnetic sensor to detect a variation of a magnetic field accompanied by deformation of the buffer member.

Abstract translation: 压力检测装置包括缓冲构件和传感器组件。 缓冲部件可通过压力变化而变形，并且包括均匀分散布置的多个磁体。 传感器组件包括至少一个磁传感器，用于检测伴随缓冲构件变形的磁场的变化。

公开(公告)号：US08258734B2

公开(公告)日：2012-09-04

申请号：US12701807

申请日：2010-02-08

Applicant: Kesatoshi Takeuchi ,  Kazuyoshi Nakamura

Inventor： Kesatoshi Takeuchi ,  Kazuyoshi Nakamura

IPC: H02P6/00

CPC classification number: H02P6/085 ,  H02P25/18 ,  H02P25/184 ,  H02P27/08

Abstract: An energy converter includes magnetic coils of N phases (N is an integer of 3 or more), and a PWM drive circuit for driving the magnetic coils of N phases, wherein the magnetic coil of each phase can be independently controlled by the PWM drive circuit.

公开(公告)号：US08183729B2

公开(公告)日：2012-05-22

申请号：US12250002

申请日：2008-10-13

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H02K16/00 ,  H02K11/00 ,  H02K21/12 ,  H02K1/22

CPC classification number: H02K16/00 ,  H02K11/215 ,  H02K15/026 ,  H02K21/24 ,  H02K29/08

Abstract: The electrically powered device is provided. The electrically powered device includes: multiple stators structured to respectively have electromagnetic coils and position sensors; a shaft fastened to the multiple stators; and multiple rotors structured to respectively have permanent magnets and arranged to rotate around the shaft; wherein the multiple rotors are connected with a driven member driven by the electrically powered device.

Abstract translation: 提供电动设备。 电动装置包括：多个定子，分别构成电磁线圈和位置传感器; 固定在多个定子上的轴; 以及多个转子，其被构造成分别具有永磁体并布置成围绕所述轴旋转; 其中所述多个转子与由所述电动装置驱动的从动构件连接。

公开(公告)号：US08072166B2

公开(公告)日：2011-12-06

申请号：US12079135

申请日：2008-03-25

Applicant: Kesatoshi Takeuchi ,  Mamoru Sugimoto ,  Isamu Sejimo ,  Kazuyoshi Nakamura

Inventor： Kesatoshi Takeuchi ,  Mamoru Sugimoto ,  Isamu Sejimo ,  Kazuyoshi Nakamura

IPC: H02P1/04

CPC classification number: H02K29/03 ,  H02K21/16 ,  H02P6/16 ,  H02P6/22 ,  H02P6/26

Abstract: The brushless motor has a first and second drive member. The first drive member is equipped with M phase coil groups each having N electromagnetic coils where M is an integer of 1 or greater and N is an integer of 1 or greater. The second drive member has a plurality of permanent magnets, and is able to move relative to the first drive member. The first drive member has 2 (M×N) magnetic body cores. Each phase electromagnetic coil is coiled on a periodically selected magnetic body core at a ratio of 1 to 2M from among the arrangement of 2 (M×N) magnetic body cores.

Abstract translation: 无刷电动机具有第一和第二驱动构件。 第一驱动部件配备有M相线圈组，每个M相线圈组具有N个电磁线圈，其中M是1或更大的整数，N是1或更大的整数。 第二驱动部件具有多个永磁体，能够相对于第一驱动部件移动。 第一驱动构件具有2个（M×N）个磁体芯。 从2（M×N）个磁体芯的布置中，每相电磁线圈以1〜2M的比例卷绕在周期性选择的磁性体芯上。

公开(公告)号：US07996692B2

公开(公告)日：2011-08-09

申请号：US12202605

申请日：2008-09-02

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The information processing apparatus equipped with a microprocessor is provided. The information processing apparatus equipped with a microprocessor includes: an operation clock signal generator that generates a frequency-variable operation clock signal supplied to the microprocessor; and a power supply voltage generator that determines a value of a power supply voltage to be supplied to the microprocessor according to a logarithm of a frequency of the operation clock signal and generates the power supply voltage.

Abstract translation: 提供了配备有微处理器的信息处理装置。 配备有微处理器的信息处理装置包括：工作时钟信号发生器，其生成提供给微处理器的可变频操作时钟信号; 以及电源电压发生器，其根据操作时钟信号的频率的对数确定要提供给微处理器的电源电压的值，并产生电源电压。

公开(公告)号：US07906930B2

公开(公告)日：2011-03-15

申请号：US12104725

申请日：2008-04-17

Applicant: Kesatoshi Takeuchi ,  Mamoru Sugimoto ,  Yojiro Okakura

Inventor： Kesatoshi Takeuchi ,  Mamoru Sugimoto ,  Yojiro Okakura

IPC: H02K41/00

CPC classification number: H02K29/08 ,  B60L3/0061 ,  B60L7/14 ,  B60L11/007 ,  B60L11/1803 ,  B60L15/007 ,  B60L15/20 ,  B60L2200/12 ,  B60L2220/14 ,  B60L2220/16 ,  B60L2220/44 ,  B60L2220/50 ,  H02K1/02 ,  H02K3/02 ,  H02K5/08 ,  H02K21/24 ,  Y02T10/641 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/72 ,  Y02T10/7275

Abstract: The brushless electric machine includes a first drive member (30U) having a plurality of permanent magnets (32U); a second drive member (10) having a plurality of electromagnetic coils and capable of movement relative to the first drive member (30U); and a third drive member (30L) disposed at the opposite side from the first drive member (30U) with the second drive member (10) therebetween, and having a fixed relative positional relationship with respect to the first drive member (30U). The second drive member (10) has magnetic sensors (40A, 40B) for detecting relative position of the first and second drive members; and a control circuit for carrying out control of the brushless electric machine utilizing the output signals of the magnetic sensors. The third drive member (30L) has at locations facing the permanent magnets of the first drive member (30U) a plurality of magnetic field strengthening members (32L) for strengthening the magnetic field at the location of the second drive member (10) in conjunction with the permanent magnets.

Abstract translation: 无刷电机包括具有多个永磁体（32U）的第一驱动部件（30U）。 具有多个电磁线圈并能够相对于第一驱动构件（30U）移动的第二驱动构件（10）; 以及第三驱动部件（30L），其与第一驱动部件（30U）相反一侧设置有第二驱动部件（10），并且与第一驱动部件（30U）具有固定的相对位置关系。 第二驱动构件（10）具有用于检测第一和第二驱动构件的相对位置的磁传感器（40A，40B） 以及利用磁传感器的输出信号进行无刷电机的控制的控制电路。 第三驱动构件（30L）在与第一驱动构件（30U）的永磁体相对的位置处具有用于在第二驱动构件（10）的位置处加强磁场的多个磁场强化构件（32L） 与永磁体。