公开(公告)号：US11367489B2

公开(公告)日：2022-06-21

申请号：US17126649

申请日：2020-12-18

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

公开(公告)号：US11361820B2

公开(公告)日：2022-06-14

申请号：US17143530

申请日：2021-01-07

Applicant: KIOXIA CORPORATION

Inventor： Tomonori Takahashi ,  Masanobu Shirakawa ,  Osamu Torii ,  Marie Takada

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US11334432B2

公开(公告)日：2022-05-17

申请号：US17092054

申请日：2020-11-06

Applicant: KIOXIA CORPORATION

Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Marie Takada

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US11322210B2

公开(公告)日：2022-05-03

申请号：US17005273

申请日：2020-08-27

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/14

Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.

公开(公告)号：US20220115070A1

公开(公告)日：2022-04-14

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US12165712B2

公开(公告)日：2024-12-10

申请号：US18362221

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Shohei Asami ,  Masamichi Fujiwara

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US12073890B2

公开(公告)日：2024-08-27

申请号：US18174916

申请日：2023-02-27

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Tsukasa Tokutomi ,  Marie Takada

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

公开(公告)号：US11967379B2

公开(公告)日：2024-04-23

申请号：US17985224

申请日：2022-11-11

Applicant: Kioxia Corporation

Inventor： Marie Takada ,  Masanobu Shirakawa

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

CPC classification number: G11C16/0433 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C11/5621 ,  G11C11/5671

Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

公开(公告)号：US11699486B2

公开(公告)日：2023-07-11

申请号：US17738069

申请日：2022-05-06

Applicant: KIOXIA CORPORATION

Inventor： Tomonori Takahashi ,  Masanobu Shirakawa ,  Osamu Torii ,  Marie Takada

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US11561736B2

公开(公告)日：2023-01-24

申请号：US17370535

申请日：2021-07-08

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Tsukasa Tokutomi

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.