公开(公告)号：US07479674B2

公开(公告)日：2009-01-20

申请号：US12034822

申请日：2008-02-21

申请人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78621

摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

公开(公告)号：US20080140344A1

公开(公告)日：2008-06-12

申请号：US12015147

申请日：2008-01-16

申请人： Hiroshi Watanabe ,  Atsuhiro Kinoshita

发明人： Hiroshi Watanabe ,  Atsuhiro Kinoshita

IPC分类号： G04F10/00

CPC分类号： G04F10/10

摘要： A system LSI including a semiconductor chip which receives power from a power supply, and an electronic timer which measures a time from an interruption of power supplying to the semiconductor chip to a resumption of power supplying to the semiconductor chip.

摘要翻译： 包括从电源接收电力的半导体芯片的系统LSI和测量从半导体芯片的供电中断恢复向半导体芯片供电的时间的电子计时器。

公开(公告)号：US20080093676A1

公开(公告)日：2008-04-24

申请号：US11892940

申请日：2007-08-28

申请人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

发明人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28079 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1203 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/7851

摘要： A semiconductor device having a field effect transistor (FET) with enhanced performance by reduction of electrical contact resistance of electrodes and resistance of the electrodes per se is disclosed. The FET includes an n-type FET having a channel region formed in a semiconductor substrate, a gate electrode insulatively overlying the channel region, and a pair of source and drain electrodes which are formed at both ends of the channel region. The source/drain electrodes are made of silicide of a first metal. An interface layer that contains a second metal is formed in the interface between the substrate and the first metal. The second metal is smaller in work function than silicide of the first metal, and the second metal silicide is less in work function than the first metal silicide. A fabrication method of the semiconductor device is also disclosed.

摘要翻译： 公开了具有通过降低电极的电接触电阻和电极本身的电阻而具有增强的性能的场效应晶体管（FET）的半导体器件。 FET包括具有形成在半导体衬底中的沟道区域，绝缘地覆盖沟道区域的栅极电极和形成在沟道区域两端的一对源极和漏极电极的n型FET。 源极/漏极由第一金属的硅化物制成。 在基板和第一金属之间的界面中形成包含第二金属的界面层。 第二金属的功函数比第一金属的硅化物小，第二金属硅化物的功函数小于第一金属硅化物。 还公开了半导体器件的制造方法。

公开(公告)号：US20080001224A1

公开(公告)日：2008-01-03

申请号：US11812609

申请日：2007-06-20

申请人： Atsuhiro Kinoshita ,  Junji Koga

发明人： Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653

摘要： A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.

摘要翻译： 提供了可以有效地抑制短通道效应和结漏电的半导体器件。 半导体器件包括场效应晶体管。 场效应晶体管包括第一导电类型的第一半导体区域，形成在栅极绝缘膜上的栅极电极以及源极和漏极电极。 场效应晶体管还包括第二导电类型的第二半导体区域。 场效应晶体管还包括具有比第二半导体区域的杂质浓度高的第二导电类型的第三半导体区域，并且形成在源电极和第一和第二半导体区域之间以及在漏电极和第一和第二半导体之间 区域和形成在栅电极的两个侧表面上的侧壁绝缘膜。 源电极和漏电极与侧壁绝缘膜分离。

公开(公告)号：US20070228486A1

公开(公告)日：2007-10-04

申请号：US11761288

申请日：2007-06-11

申请人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yoshinori Tsuchiya ,  Toshifumi Irisawa ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/768

CPC分类号： H01L29/4908 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/785

摘要： A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0≦c≦1, a≠c).

摘要翻译： 半导体器件包括形成在衬底上的n型和p型半导体器件，n型器件包括形成在衬底上的n沟道区，n型源极和漏极区彼此相对形成， 沟道区域，形成在n沟道区上的第一栅极绝缘体和形成在第一栅极绝缘体上的第一栅电极，并且包括金属M和第一族IV元素Si 1-a的化合物， （0 <= a <= 1），p型器件包括形成在衬底上的p沟道区域，彼此相对形成的p型源极和漏极区域 在其间插入p沟道区域，形成在p沟道区域上的第二栅极绝缘体和形成在第二栅极绝缘体上的第二栅电极，并且包括金属M和第二IV族元素Si _c）。

公开(公告)号：US20050212055A1

公开(公告)日：2005-09-29

申请号：US11081348

申请日：2005-03-16

申请人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/417 ,  H01L21/00 ,  H01L21/336 ,  H01L29/76 ,  H01L29/772 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78621

摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

公开(公告)号：US20050093033A1

公开(公告)日：2005-05-05

申请号：US10933333

申请日：2004-09-03

申请人： Atsuhiro Kinoshita ,  Junji Koga

发明人： Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7839 ,  H01L29/78618 ,  H01L29/78645

摘要： A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

摘要翻译： 场效应晶体管包括形成沟道区域的第一半导体区域，绝缘地设置在第一半导体区域上方的栅电极，形成为在沟道纵向方向夹着第一半导体区域的源电极和漏电极，以及形成在第一半导体区域之间的第二半导体区域 半导体区域和源极和漏极，并且具有高于第一半导体区域的杂质浓度。 通道长度方向上的第二半导体区域的厚度被设定为等于或小于由杂质浓度确定的耗尽层宽度的值，使得第二半导体区域在无电压施加状态下耗尽。

公开(公告)号：US08710573B2

公开(公告)日：2014-04-29

申请号：US12831323

申请日：2010-07-07

申请人： Atsuhiro Kinoshita ,  Hiroshi Watanabe ,  Fumitaka Arai

发明人： Atsuhiro Kinoshita ,  Hiroshi Watanabe ,  Fumitaka Arai

IPC分类号： H01L29/788

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

公开(公告)号：US20130076550A1

公开(公告)日：2013-03-28

申请号：US13536085

申请日：2012-06-28

申请人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

发明人： Takao MARUKAME ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

IPC分类号： H03M1/34

CPC分类号： H03M1/1061 ,  H01L27/22 ,  H01L43/08 ,  H03M1/365

摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

摘要翻译： 根据实施例，模数转换器包括电压产生单元和多个比较器。 电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。 多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。 多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

公开(公告)号：US08299507B2

公开(公告)日：2012-10-30

申请号：US12714841

申请日：2010-03-01

申请人： Tatsuo Shimizu ,  Atsuhiro Kinoshita

发明人： Tatsuo Shimizu ,  Atsuhiro Kinoshita

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28176 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31604 ,  H01L28/75 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7881

摘要： It is made possible to optimize the effective work function of the metal for a junction and suppress the resistance as far as possible at the interface between a semiconductor or a dielectric material and a metal. A semiconductor device includes: a semiconductor film; a Ti oxide film formed on the semiconductor film, and including at least one element selected from the group consisting of V, Cr, Mn, Fe, Co, Ni, Nb, Mo, Tc, Ru, Rh, Pd, Ta, W, Re, Os, Ir, and Pt; and a metal film formed on the Ti oxide film.

摘要翻译： 可以优化用于结的金属的有效功函数，并且尽可能地在半导体或电介质材料与金属之间的界面处抑制电阻。 半导体器件包括：半导体膜; 形成在所述半导体膜上的Ti氧化膜，并且包括选自V，Cr，Mn，Fe，Co，Ni，Nb，Mo，Tc，Ru，Rh，Pd，Ta，W中的至少一种元素， Re，Os，Ir和Pt; 以及形成在Ti氧化物膜上的金属膜。