公开(公告)号：US11282581B1

公开(公告)日：2022-03-22

申请号：US17140825

申请日：2021-01-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Sung Chen ,  Chien-Fu Huang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08

Abstract: A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.

公开(公告)号：US09933977B1

公开(公告)日：2018-04-03

申请号：US15346790

申请日：2016-11-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Han-Sung Chen ,  Chung-Kuang Chen

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/3431 ,  G11C16/3495

Abstract: A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.

公开(公告)号：US09471485B2

公开(公告)日：2016-10-18

申请号：US13926633

申请日：2013-06-25

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Han-Sung Chen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.

Abstract translation: 一种用于维护数据集的方法包括将数据集的基本副本存储在具有第一写入速度的第一非易失性存储器中，将具有第一非易失性存储器的第一变化数据集中的数据集的改变存储在具有第 第二写入速度，并通过读取基本副本和更改来生成数据集的当前副本。 如果达到第一改变数据集中的阈值数目，则将第一变化数据集的部分或全部移动到第一非易失性存储器中的第二变化数据集中，其中生成步骤包括读取第二变化 数据集。 如果达到第二改变数据集中的阈值数目，则通过读取基本副本和第一和第二非易失性存储器中的改变来生成当前副本。

公开(公告)号：US09349469B2

公开(公告)日：2016-05-24

申请号：US14505297

申请日：2014-10-02

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C16/3459

Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.

Abstract translation: 感测电路耦合到存储器阵列的位线。 耦合到感测电路的控制电路控制存储器单元的编程操作。 在编程存储器阵列中的存储单元的程序阶段之后，在程序验证阶段中，控制电路使得感测电路在程序验证阶段期间多次检测存储在存储器单元上的数据。 多次包括来自存储器单元的第一次感测数据和来自存储器单元的第二时间感测数据。

公开(公告)号：US20160103763A1

公开(公告)日：2016-04-14

申请号：US14513899

申请日：2014-10-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chung-Hsiung Hung

IPC: G06F12/06

CPC classification number: G11C16/10 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

Abstract translation: 该技术的一个方面是存储器件，其包括多个页缓冲器和控制电路。 多个页缓冲器电路中的不同页缓冲器电路被耦合到存储器阵列中的多个位线中的不同位线。 控制电路响应于程序命令来对存储器阵列中的多个单元进行编程，通过多个页缓冲器电路同时针对耦合到多个单元的不同位线同时设置不同的目标电压。

公开(公告)号：US20160099069A1

公开(公告)日：2016-04-07

申请号：US14505297

申请日：2014-10-02

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C16/3459

Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.

Abstract translation: 感测电路耦合到存储器阵列的位线。 耦合到感测电路的控制电路控制存储器单元的编程操作。 在编程存储器阵列中的存储单元的程序阶段之后，在程序验证阶段中，控制电路使得感测电路在程序验证阶段期间多次检测存储在存储器单元上的数据。 多次包括来自存储器单元的第一次感测数据和来自存储器单元的第二时间感测数据。

公开(公告)号：US09147487B2

公开(公告)日：2015-09-29

申请号：US13688623

申请日：2012-11-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/04 ,  G11C16/30 ,  G11C11/56 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/30 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3454

Abstract: A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range.

Abstract translation: 一种用于编程存储器件的存储器单元的方法包括以下步骤。 设置多个循环数范围。 确定具有漏极端子的存储单元通过程序验证的多个循环数范围中的特定的一个。 向漏极端子施加偏置电压以对存储器单元进行编程，其中偏置电压随特定周期数范围变化。

公开(公告)号：US20150212875A1

公开(公告)日：2015-07-30

申请号：US14167927

申请日：2014-01-29

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1048 ,  H03M13/151 ,  H03M13/356 ,  H03M13/6505 ,  H03M13/6561

Abstract: A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.

Abstract translation: 用于操作存储器的方法包括接收输入数据集，为输入数据集中的数据保存第一级纠错码ECC，为数据集中的数据的多个第二级组保存第二级ECC，存储 存储器中的数据集，并测试数据集以确定是使用第一级ECC还是第二级ECC。 该方法包括如果使用第一级ECC，则存储能够使用第一级ECC的标志，否则如果使用第二级ECC，则存储允许使用第二级ECC的标志。 该方法包括将第二级ECC存储在替换ECC存储器中，并将指示第二级ECC的位置的指针存储在替换ECC存储器中。

公开(公告)号：US20140281175A1

公开(公告)日：2014-09-18

申请号：US14265400

申请日：2014-04-30

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/00 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/10 ,  G11C16/105 ,  G11C2211/5648

Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.

Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。

公开(公告)号：US20140269074A1

公开(公告)日：2014-09-18

申请号：US13950942

申请日：2013-07-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lung Yi KUO ,  Hsin Yi Ho ,  Chun Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen ,  Shih-Chou Juan

IPC: G11C16/10 ,  G11C29/04

CPC classification number: G11C16/10 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/4402

Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。