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    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings
    31.
    发明申请
    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings 审中-公开
    使用薄介电涂层形成电隔离结构的方法

    公开(公告)号：US20160258075A1

    公开(公告)日：2016-09-08

    申请号：US15091537

    申请日：2016-04-05

    Applicant: Microfabrica Inc.

    Inventor： Dennis R. Smalley ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard

    IPC: C25D1/00 ,  H05K3/46 ,  C25D1/20

    CPC classification number: A61N1/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D1/20 ,  C25D5/022 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/07357 ,  G01R31/2886 ,  H05K3/467 ,  H05K3/4682

    Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

    Abstract translation: 用于生产多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层，包括用于提供将第一导电材料的至少一部分与 （1）第一导电材料的其它部分，（2）第二导电材料或（3）另一种电介质材料，并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中，每个单独层的部分被电介质材料包封，而在其它实施例中，材料的不同区域之间的边界通过电介质屏障彼此隔离。

    Miniature RF and Microwave Components and Methods for Fabricating Such Components
    32.
    发明申请
    Miniature RF and Microwave Components and Methods for Fabricating Such Components 有权
    微型射频和微波元件及其制造方法

    公开(公告)号：US20150311575A1

    公开(公告)日：2015-10-29

    申请号：US14675147

    申请日：2015-03-31

    Applicant: Microfabrica Inc.

    Inventor： Elliott R. Brown ,  John D. Evans ,  Christopher A. Bang ,  Adam L. Cohen ,  Michael S. Lockard ,  Dennis R. Smalley ,  Morton Grosser

    IPC: H01P3/06 ,  C25D5/02

    CPC classification number: H01P3/06 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10

    Abstract: RF and microwave radiation directing or controlling components are provided that may be monolithic, that may be formed from a plurality of electrodeposition operations and/or from a plurality of deposited layers of material, that may include switches, inductors, antennae, transmission lines, filters, hybrid couplers, antenna arrays and/or other active or passive components. Components may include non-radiation-entry and non-radiation-exit channels that are useful in separating sacrificial materials from structural materials. Preferred formation processes use electrochemical fabrication techniques (e.g. including selective depositions, bulk depositions, etching operations and planarization operations) and post-deposition processes (e.g. selective etching operations and/or back filling operations).

    Abstract translation: 提供RF和微波辐射引导或控制部件，其可以是单片的，其可以由多个电沉积操作和/或从多个沉积的材料层形成，其可以包括开关，电感器，天线，传输线，滤波器 ，混合耦合器，天线阵列和/或其他主动或无源部件。 部件可以包括用于将牺牲材料与结构材料分离的非辐射入口和非辐射出口通道。 优选的形成方法使用电化学制造技术（例如包括选择性沉积，体积沉积，蚀刻操作和平坦化操作）和后沉积工艺（例如选择性蚀刻操作和/或反向填充操作）。

    Methods and Apparatus for Forming Multi-Layer Structures Including Use of A Sacrificial Patternable Mold Material
    33.
    发明申请
    Methods and Apparatus for Forming Multi-Layer Structures Including Use of A Sacrificial Patternable Mold Material 审中-公开
    形成多层结构的方法和装置，包括使用可牺牲图案的模具材料

    公开(公告)号：US20150308006A1

    公开(公告)日：2015-10-29

    申请号：US14676716

    申请日：2015-04-01

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Jill R. Thomassian ,  Michael S. Lockard ,  Marvin M. Kilgo, III ,  Uri Frodis ,  Dennis R. Smalley

    IPC: C25D1/00 ,  C25D5/10 ,  C25D5/02

    CPC classification number: C25D1/003 ,  C25D1/00 ,  C25D1/20 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D5/14 ,  C25D5/48 ,  C25D5/50

    Abstract: Numerous electrochemical fabrication methods and apparatus are provided for producing multi-layer structures (e.g. having meso-scale or micro-scale features) from a plurality of layers of deposited materials using adhered masks (e.g. formed from liquid photoresist or dry film), where two or more materials may be provided per layer where at least one of the materials is a structural material and one or more of any other materials may be a sacrificial material which will be removed after formation of the structure. Materials may comprise conductive materials that are electrodeposited or deposited in an electroless manner. In some embodiments special care is undertaken to ensure alignment between patterns formed on successive layers.

    Abstract translation: 提供了多种电化学制造方法和装置，用于使用粘附的掩模（例如由液体光致抗蚀剂或干膜形成）从多层沉积材料制备多层结构（例如具有中尺度或微尺度特征），其中两个 或者可以在每层中提供更多的材料，其中至少一种材料是结构材料，并且任何其它材料中的一种或多种可以是在形成结构之后被去除的牺牲材料。 材料可以包括以无电解方式电沉积或沉积的导电材料。 在一些实施例中，特别注意确保在连续层上形成的图案之间的对准。

    Microprobe Tips and Methods for Making
    34.
    发明申请
    Microprobe Tips and Methods for Making 审中-公开
    微型技巧和制作方法

    公开(公告)号：US20150108002A1

    公开(公告)日：2015-04-23

    申请号：US14572472

    申请日：2014-12-16

    Applicant: Microfabrica Inc.

    Inventor： Kieun Kim ,  Adam L. Cohen ,  Willa M. Larsen ,  Richard Chen ,  Ananda H. Kumar ,  Ezekiel J.J. Kruglick ,  Vacit Arat ,  Gang Zhang ,  Michael S. Lockard ,  Christopher A. Bang ,  Jeffrey A. Thompson

    IPC: C25D5/02 ,  C25D7/00

    CPC classification number: C25D1/003

    Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate. Probe tip patterning may occur in a variety of different ways, including, for example, via molding in patterned holes that have been isotropically or anisotropically etched silicon, via molding in voids formed in exposed photoresist, via molding in voids in a sacrificial material that have formed as a result of the sacrificial material mushrooming over carefully sized and located regions of dielectric material, via isotropic etching of the tip material around carefully sized and placed etching shields, via hot pressing, and the like.

    Abstract translation: 本发明的实施例涉及形成具有各种构造的微探针尖元件。 在一些实施例中，尖端由与探针本身相同的建筑材料形成，而在其它实施例中，尖端可以由不同的材料形成和/或可以包括涂层材料。 在一些实施例中，尖端在探针的主要部分之前形成，并且尖端形成在临时衬底附近或与临时衬底接触。 探针尖端图案化可以以各种不同的方式发生，包括例如通过在各向异性或各向异性地蚀刻硅的图案化孔中模制，通过在曝光的光致抗蚀剂中形成的空隙中模制，通过在牺牲材料中的空隙中模制， 由于牺牲材料通过电介质材料的细小尺寸和定位的区域，经由热压等等仔细地尺寸和放置的蚀刻屏蔽部分上的尖端材料的各向同性蚀刻而形成。

    Methods of Forming Three-Dimensional Structures Having Reduced Stress and/or Curvature
    35.
    发明申请
    Methods of Forming Three-Dimensional Structures Having Reduced Stress and/or Curvature 有权
    形成具有减小的应力和/或曲率的三维结构的方法

    公开(公告)号：US20140238865A1

    公开(公告)日：2014-08-28

    申请号：US14194564

    申请日：2014-02-28

    Applicant: Microfabrica Inc.

    Inventor： Ananda H. Kumar ,  Jorge S. Alberron ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

    IPC: B81C1/00 ,  C25D5/02

    CPC classification number: B81C1/00666 ,  C25D5/022

    Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

    Abstract translation: 用于生产单层或多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层包括当结构被释放时减少应力和/或曲率失真的操作 牺牲材料，其在形成期间包围它，并且可能当从其形成的基底释放时。 呈现了六个主要实施例的组，它们分为十一个主要实施例。 一些实施例尝试去除应力以最小化失真，而另一些实施例试图平衡应力以最小化失真。

    Method for Fabricating Miniature Structures or Devices such as RF and Microwave Components
    36.
    发明申请
    Method for Fabricating Miniature Structures or Devices such as RF and Microwave Components 有权
    用于制造微型结构或诸如RF和微波组件的设备的方法

    公开(公告)号：US20140197904A1

    公开(公告)日：2014-07-17

    申请号：US14194592

    申请日：2014-02-28

    Applicant: Microfabrica Inc.

    Inventor： Elliott R. Brown ,  John D. Evans ,  Christopher A. Bang ,  Adam L. Cohen ,  Michael S. Lockard ,  Dennis R. Smalley ,  Morton Grosser

    IPC: H01P1/202 ,  H01P11/00

    CPC classification number: H01P1/202 ,  B33Y10/00 ,  B33Y70/00 ,  B81B2201/042 ,  C25D1/003 ,  G01P15/0802 ,  G01P15/125 ,  H01P3/06 ,  H01P5/183 ,  H01P11/00 ,  H01P11/005 ,  H01P11/007 ,  H05K3/4647 ,  Y10T29/49002 ,  Y10T29/49016 ,  Y10T29/49018

    Abstract: Multi-layer, multi-material fabrication methods include depositing at least one structural material and at least one sacrificial material during the formation of each of a plurality of layers wherein deposited materials for each layer are planarized to set a boundary level for the respective layer and wherein during formation of at least one layer at least three materials are deposited with a planarization operation occurring before deposition of the last material to set a planarization level above the layer boundary level and wherein a planarization occurs after deposition of the last material level above the layer boundary level and wherein a planarization occurs after deposition of the last material whereby the boundary level for the layer is set. Some formation processes use electrochemical fabrication techniques (e.g. including selective depositions, bulk depositions, etching operations and planarization operations) and post-deposition processes (e.g. selective etching operations and/or back filling operations).

    Abstract translation: 多层多材料制造方法包括在形成多个层期间沉积至少一种结构材料和至少一种牺牲材料，其中每层的沉积材料被平坦化以设定各层的边界水平， 其中在形成至少一个层期间，沉积至少三种材料，其中在沉积最终材料之前发生的平坦化操作，以将平坦化水平设置在层边界水平之上，并且其中在沉积层上方的最后材料层之后发生平坦化 并且其中在沉积最后的材料之后发生平坦化，由此设置该层的边界水平。 一些形成方法使用电化学制造技术（例如包括选择性沉积，体积沉积，蚀刻操作和平面化操作）和后沉积工艺（例如选择性蚀刻操作和/或反向填充操作）。

    Methods of Forming Parts Using Laser Machining
    37.
    发明申请
    Methods of Forming Parts Using Laser Machining 有权
    使用激光加工形成零件的方法

    公开(公告)号：US20140197145A1

    公开(公告)日：2014-07-17

    申请号：US14156437

    申请日：2014-01-15

    Applicant: Microfabrica Inc.

    Inventor： Arun S. Veeramani ,  Heath A. Jensen ,  Uri Frodis ,  Christopher G. Wiita ,  Michael S. Lockard ,  Irina Boguslavsky ,  Pavel Lembrikov ,  Dennis R. Smalley ,  Richard T. Chen

    IPC: B23K26/38

    CPC classification number: B23K26/38 ,  B23K26/0624 ,  B23K26/18 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  G01R1/06738 ,  G01R1/06744 ,  G01R3/00

    Abstract: Embodiments are directed to the formation micro-scale or millimeter scale structures or method of making such structures wherein the structures are formed from at least one sheet structural material and may include additional sheet structural materials or deposited structural materials wherein all or a portion of the patterning of the structural materials occurs via laser cutting. In some embodiments, selective deposition is used to provide a portion of the patterning. In some embodiments the structural material or structural materials are bounded from below by a sacrificial bridging material (e.g. a metal) and possibly from above by a sacrificial capping material (e.g. a metal).

    Abstract translation: 实施例涉及形成微尺度或毫米级结构或制造这种结构的方法，其中结构由至少一个片状结构材料形成，并且可以包括附加的片状结构材料或沉积的结构材料，其中所有或部分图案化 的结构材料通过激光切割发生。 在一些实施例中，使用选择性沉积来提供图案化的一部分。 在一些实施例中，结构材料或结构材料由牺牲桥接材料（例如金属）从下方限定，并且可能由上面由牺牲性封盖材料（例如金属）限定。

    Probe Arrays and Improved Methods for Making and Using Longitudinal Deformation of Probe Preforms
    39.
    发明公开
    Probe Arrays and Improved Methods for Making and Using Longitudinal Deformation of Probe Preforms 审中-公开

    公开(公告)号：US20240094261A1

    公开(公告)日：2024-03-21

    申请号：US17401252

    申请日：2021-08-12

    Applicant: Microfabrica Inc.

    Inventor： Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

    IPC: G01R3/00 ,  G01R1/067

    CPC classification number: G01R3/00 ,  G01R1/06722 ,  G01R1/06761

    Abstract: Probes for testing (e.g. wafer level testing or socket level testing) of electronic devices (e.g. semiconductor devices) and more particularly, arrays of such probes are provided. Probes are formed by initially fabricating probe preforms in batch with bases and/or ends located in array patterns, directly or indirectly on one or more build substrates with the arrayed preforms being in a longitudinally compressed state and whereafter the preforms are longitudinally plastically deformed to yield probes or partially formed probes with extended longitudinal lengths. Probes may be formed with deformable spring elements formed from one or more single layers which are joined by vertical elements located on other layers or they may be formed by spring elements that are formed as multi-layer structures. Arrays may include probe preforms with laterally overlapping or interlaced structures (but longitudinally displaced) which may remain laterally overlapping or become laterally displaced upon plastic deformation.

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