公开(公告)号：US20240069735A1

公开(公告)日：2024-02-29

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US11728006B2

公开(公告)日：2023-08-15

申请号：US17747598

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Chun Sum Yeung ,  Xiangang Luo

IPC: G11C29/00 ,  G11C29/52 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C29/44 ,  G11C29/52 ,  G11C29/808 ,  G11C29/886

Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.

公开(公告)号：US20230205690A1

公开(公告)日：2023-06-29

申请号：US17646253

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Min Rui Ma

IPC: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

CPC classification number: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/0483 ,  G06F2212/1032

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

公开(公告)号：US20230015066A1

公开(公告)日：2023-01-19

申请号：US17378970

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Chun Sum Yeung ,  Kulachet Tanpairoj

IPC: G06F3/06

Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

公开(公告)号：US11513889B2

公开(公告)日：2022-11-29

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210193231A1

公开(公告)日：2021-06-24

申请号：US16807739

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Chun Sum Yeung

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/10

Abstract: A processing device, operatively coupled with the memory device, is configured to receive a read request identifying data stored in a data unit of the memory device. The processing device further identifies a set of data units with which the data unit is associated, the set of data units is one of a plurality of sets of data units, and each data unit in the set of data units was programmed within a period of time associated with the set of data units. The processing device also determines a read voltage level of the set of data units, each of the plurality of sets of data units has a separate read voltage level. The processing device further performs a read operation on the data unit of the memory device using the read voltage level of the set of data units.

公开(公告)号：US11017870B1

公开(公告)日：2021-05-25

申请号：US16798832

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Devin M. Batutis ,  Avinash Rajagiri ,  Sheng-Huang Lee ,  Chun Sum Yeung ,  Harish R. Singidi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

公开(公告)号：US20240338139A1

公开(公告)日：2024-10-10

申请号：US18748715

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wai Leong Chin ,  Francis Chee Khai Chew ,  Trismardawi Tanadi ,  Chun Sum Yeung ,  Lawrence Dumalag ,  Ekamdeep Singh

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0646 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7206

Abstract: A memory sub-system causing execution of a first wordline leakage test of a first wordline group of a set of wordline groups of a memory block in response to determining a temperature of the memory block is within a threshold temperature range. A first result of the first wordline leakage test is determined. A second wordline leakage test of a second wordline group is caused to be executed and a second result is determined. A determination is made that the first result of the first wordline leakage test of the first wordline group satisfies a first condition. A determination is made that the second result of the second wordline leakage test of the second wordline group satisfies a second condition. In response to satisfaction of the conditions, an action is executed.

公开(公告)号：US12111724B2

公开(公告)日：2024-10-08

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1076

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20240312554A1

公开(公告)日：2024-09-19

申请号：US18600360

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Zhongyuan Lu

IPC: G11C29/52 ,  G11C11/406 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C11/40622 ,  G11C29/022

Abstract: Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.