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    Apparatuses and methods for segmented SGS lines
    32.
    发明授权
    Apparatuses and methods for segmented SGS lines 有权
    分段SGS线的装置和方法

    公开(公告)号：US09460792B2

    公开(公告)日：2016-10-04

    申请号：US14518807

    申请日：2014-10-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Feng Pan ,  Jaekwan Park ,  Ramin Ghodsi

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24

    CPC classification number: G11C16/0483 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.

    Abstract translation: 描述了分段SGS线的装置和方法。 示例性装置可以包括存储器块的第一和第二多个存储器子块。 该装置可以包括与第一多个存储器子块相关联的第一选择栅极控制线和与第二多个存储器子块相关联的第二选择栅极控制线。 第一选择栅极控制线可以耦合到第一多个存储器子块的第一多个选择栅极开关。 第二选择栅极控制线可以耦合到第二多个存储器子块的第二多个选择栅极开关。 第一和第二多个选择栅极开关可以耦合到源极。 该装置可以包括与每个第一和第二多个存储器子块相关联的多个存储器访问线。

    APPARATUSES AND METHODS AND FOR PROVIDING POWER RESPONSIVE TO A POWER LOSS
    35.
    发明申请
    APPARATUSES AND METHODS AND FOR PROVIDING POWER RESPONSIVE TO A POWER LOSS 有权
    设备和方法，并提供电力损失的电力

    公开(公告)号：US20140115373A1

    公开(公告)日：2014-04-24

    申请号：US13657444

    申请日：2012-10-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ramin Ghodsi

    IPC: G06F1/26

    CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F1/3268 ,  G06F13/1694

    Abstract: Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss.

    Abstract translation: 本文公开了用于提供响应于功率损耗的功率的装置和方法。 功率芯片可以包括功率传感器，写命令控制逻辑和阵列。 功率传感器可以被配置为检测电源的功率损耗并且至少部分地响应于检测电源的功率损耗而提供功率损耗控制信号。 写命令控制逻辑可以耦合到功率传感器，并且可以被配置为接收功率损耗控制信号。 写命令控制逻辑还可以被配置为至少部分地响应于接收到功率损耗控制信号来提供写入命令。 阵列可以包括被配置为存储电力并被进一步配置成在功率损耗期间提供功率的多个电容器。

    HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY
    36.
    发明申请
    HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY 有权

    公开(公告)号：US20250111884A1

    公开(公告)日：2025-04-03

    申请号：US18915265

    申请日：2024-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Ramin Ghodsi

    IPC: G11C29/42 ,  G11C15/04 ,  G11C29/12 ,  G11C29/20

    Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

    Memories for determining data states of memory cells
    37.
    发明授权
    Memories for determining data states of memory cells 有权

    公开(公告)号：US11508447B2

    公开(公告)日：2022-11-22

    申请号：US17344141

    申请日：2021-06-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Ramin Ghodsi

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

    Abstract: Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.

    HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY
    38.
    发明申请
    HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY 有权

    公开(公告)号：US20220359033A1

    公开(公告)日：2022-11-10

    申请号：US17729973

    申请日：2022-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Ramin Ghodsi

    IPC: G11C29/42 ,  G11C29/12 ,  G11C29/20 ,  G11C15/04

    Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

    I/O BUFFER OFFSET MITIGATION
    39.
    发明申请
    I/O BUFFER OFFSET MITIGATION 有权

    公开(公告)号：US20210065807A1

    公开(公告)日：2021-03-04

    申请号：US17096055

    申请日：2020-11-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Qiang Tang ,  Ramin Ghodsi

    IPC: G11C16/10 ,  G11C16/04 ,  H03K19/00 ,  G11C16/26 ,  H03K19/0185 ,  G11C29/02 ,  G11C29/50 ,  G11C7/10

    Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

    Apparatuses and methods for reducing read disturb
    40.
    发明授权
    Apparatuses and methods for reducing read disturb 有权

    公开(公告)号：US10854301B2

    公开(公告)日：2020-12-01

    申请号：US16182355

    申请日：2018-11-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24

    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

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