公开(公告)号：US09076535B2

公开(公告)日：2015-07-07

申请号：US13936729

申请日：2013-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yen-Hao Shih

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578

Abstract: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions.

Abstract translation: 为存储器提供了基于薄膜晶体管的存储器件中的电荷载体源。 电荷载流子源可以包括具有第一和第二端子的二极管。 经由第一开关耦合到位线的NAND串通过第二开关耦合到第二端，耦合到二极管的第一端。 分别可驱动的第一和第二电源线分别耦合到二极管的第一和第二端子。 包括耦合到第一和第二电源线的电路，其被配置为根据包括正向偏置条件和反向偏置条件的操作模式，以不同的偏置条件偏置第一和第二电源线。

公开(公告)号：US09053803B2

公开(公告)日：2015-06-09

申请号：US14060645

申请日：2013-10-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: G11C5/06 ,  G11C16/24 ,  H01L23/528 ,  H01L21/768 ,  G11C16/04

CPC classification number: H01L23/528 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork architecture comprises a handle portion and prong portions extending from the handle portion. The fork architecture comprises a stacked structure and a dielectric layer. The dielectric layer is between the first conductive structure and the handle portion of the stacked structure.

Abstract translation: 提供集成电路及其制造和操作方法。 集成电路包括叉结构和第一导电结构。 叉结构包括手柄部分和从手柄部分延伸的叉形部分。 叉结构包括堆叠结构和电介质层。 介电层位于第一导电结构和堆叠结构的手柄部分之间。

公开(公告)号：US08981567B2

公开(公告)日：2015-03-17

申请号：US13948508

申请日：2013-07-23

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/115 ,  H01L29/417 ,  H01L29/788 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

公开(公告)号：US12254934B2

公开(公告)日：2025-03-18

申请号：US18180874

申请日：2023-03-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Chih-Chang Hsieh

IPC: G11C17/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

公开(公告)号：US20230082361A1

公开(公告)日：2023-03-16

申请号：US17475932

申请日：2021-09-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

公开(公告)号：US11183511B2

公开(公告)日：2021-11-23

申请号：US16257165

申请日：2019-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/115 ,  H01L27/105 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

公开(公告)号：US10593697B1

公开(公告)日：2020-03-17

申请号：US16540275

申请日：2019-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang ,  Kuo-Pin Chang

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.

公开(公告)号：US10535673B2

公开(公告)日：2020-01-14

申请号：US15996617

申请日：2018-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue

IPC: H01L27/11 ,  H01L27/11556 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11519

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

公开(公告)号：US10340222B2

公开(公告)日：2019-07-02

申请号：US15791521

申请日：2017-10-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/528 ,  H01L27/11556 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11521 ,  H01L21/3205 ,  H01L21/02

Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.

公开(公告)号：US20190122983A1

公开(公告)日：2019-04-25

申请号：US15791521

申请日：2017-10-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/528 ,  H01L27/11521 ,  H01L27/11556 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A stair contact structure, a manufacturing method of a stair contact structure, and a memory structure are provided. The stair contact structure includes several layers of stacking structures and a first etch stop layer. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. The first etch stop layer penetrates through the stacking structures and extends along a first horizontal direction. The conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages.