公开(公告)号：US09396966B1

公开(公告)日：2016-07-19

申请号：US14582924

申请日：2014-12-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/32139 ,  H01L21/0338

Abstract: A patterning method and a patterned material layer are provided. After providing a substrate including a material layer, a hard mask layer including trenches extending in a first direction is formed over the material layer. A filling material layer is formed on the hard mask layer to cover the hard mask layer and fills in the trenches. A mask layer in a grid pattern is formed on the filling material layer. The mask layer includes first grid lines extending in the first direction and second grid lines extending in a second direction, and each of the underlying trench is located between two most adjacent first grid lines. The material layer is etched with the mask layer as an etching mask to form a patterned material layer including a plurality of first holes and a plurality of second holes.

Abstract translation: 提供了图案化方法和图案化材料层。 在提供包括材料层的基板之后，在材料层上形成包括沿第一方向延伸的沟槽的硬掩模层。 在硬掩模层上形成填充材料层以覆盖硬掩模层并填充在沟槽中。 在填充材料层上形成网格图案的掩模层。 掩模层包括沿第一方向延伸的第一栅格线和沿第二方向延伸的第二栅格线，并且每个下面的沟槽位于两个最相邻的第一栅格线之间。 用掩模层作为蚀刻掩模蚀刻材料层以形成包括多个第一孔和多个第二孔的图案化材料层。

公开(公告)号：US09209016B1

公开(公告)日：2015-12-08

申请号：US14513922

申请日：2014-10-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/67

CPC classification number: H01L21/02282 ,  H01L21/02296 ,  H01L21/6715

Abstract: A wafer-level coating method and a coating system are provided. A strip-shaped sprayer is disposed above the wafer, and a length of the strip-shaped sprayer is larger than a diameter of the wafer. Then, a coating process is performed by spraying a material from the strip-shaped sprayer to form a material layer covering a top surface of the wafer and moving the strip-shaped sprayer relative to the wafer in a direction vertical to a length direction of the strip-shaped sprayer for at least a distance equal to or larger than the diameter of the wafer. Next, the moving strip-shaped sprayer and the spraying of the material are stopped after the material layer is formed.

Abstract translation: 提供了晶片级涂布方法和涂布系统。 条形喷雾器设置在晶片上方，并且条形喷雾器的长度大于晶片的直径。 然后，通过喷涂来自带状喷雾器的材料来形成涂覆工艺，以形成覆盖晶片顶表面的材料层，并且使该带状喷雾器相对于晶片在垂直于 条形喷雾器至少等于或大于晶片直径的距离。 接下来，在形成材料层之后停止移动的带状喷雾器和材料的喷射。

公开(公告)号：US20150187786A1

公开(公告)日：2015-07-02

申请号：US14143767

申请日：2013-12-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L27/115 ,  H01L21/768 ,  G11C5/06 ,  H01L23/528

CPC classification number: H01L27/11565 ,  G11C5/063 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11568 ,  H01L27/11575

Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.

Abstract translation: 描述形成分开的窄线的方法。 目标层形成在衬底上。 在目标层上形成基本图案。 目标线图案和目标线图案的端部之间的连接图案在基底图案的侧壁上形成为间隔物。 基本图案被删除。 目标线图案和连接图案被传送到目标层以在目标线的端部之间形成目标线和连接段。 每个连接段的至少一部分被去除以断开目标线，而衬底的其它区域经受图案化去除处理。

公开(公告)号：US20250096147A1

公开(公告)日：2025-03-20

申请号：US18470421

申请日：2023-09-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chiung Jung Tu ,  Chih-Hao Huang ,  Yu-Lin Liu ,  Chin-Cheng Yang

IPC: H01L23/544

Abstract: An overlay mark includes a previous layer mark and a current layer mark. The previous layer mark includes a plurality of first work zones. Each first working zone includes a first sub-region and a second sub-region, wherein the first sub-region is closer to a center point of the previous layer mark than the second sub-region. The previous layer mark includes a first mark and an auxiliary mark respectively in the first sub-region and the second sub-region of each first working zone. The current layer mark includes a plurality of second working zones. Each second working zone includes a first sub-region and a second sub-region. The current layer mark includes a second mark disposed in the second sub-region of each second working zone. The overlay mark may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20240071906A1

公开(公告)日：2024-02-29

申请号：US17900587

申请日：2022-08-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/768

Abstract: A semiconductor structure including a substrate and a pad structure is provided. The pad structure is located on the substrate. The pad structure includes material pairs and pads. The material pairs are stacked on the substrate to form a stair step structure. Each of the material pairs includes a conductive layer and a dielectric layer located on the conductive layer. Each of the pads includes a conductive pillar and a pad layer. The conductive pillar is embedded in the material pair and is connected to the conductive layer of the material pair. The pad layer is located on the conductive pillar.

公开(公告)号：US10497566B1

公开(公告)日：2019-12-03

申请号：US16012608

申请日：2018-06-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang ,  Chi-Hao Huang ,  Wei-Hung Wang

IPC: H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/105

Abstract: A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.

公开(公告)号：US10192824B2

公开(公告)日：2019-01-29

申请号：US15483646

申请日：2017-04-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L23/528 ,  H01L27/105 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: An edge structure for multiple layers of devices including stacked multiple unit layers includes first and second stair structures. The first stair structure is at a first direction of the devices where device contacts are formed, including first edge portions of the unit layers at the first direction, of which the borders gradually retreat with increase of level height. The elevation angle from the border of the first edge portion of the bottom unit layer to that of the top one is a first angle. The second stair structure includes second edge portions of the unit layers at a second direction. The variation of border position of the second edge portion with increase of level height is irregular. The elevation angle from the border of the second edge portion of the bottom unit layer to that of the top one is a second angle larger than the first angle.

公开(公告)号：US20180102281A1

公开(公告)日：2018-04-12

申请号：US15289231

申请日：2016-10-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang

IPC: H01L21/768 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  G11C16/08

CPC classification number: H01L21/76816 ,  G11C16/08 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.

公开(公告)号：US20170084597A1

公开(公告)日：2017-03-23

申请号：US14861933

申请日：2015-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang ,  Chia-Hua Lin ,  Chih-Hao Huang

IPC: H01L27/02 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L27/0207 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70616 ,  G06F17/5072 ,  H01L29/0657

Abstract: A structure of a patterned material layer including separate patterns arranged in rows and columns is described. The separate patterns in at least one row including the outmost row each have a larger dimension in the column direction than the separate patterns in the other rows. The separate patterns in at least one column including the outmost column each have a larger dimension in the row direction than the separate patterns in the other columns.

公开(公告)号：US09412612B2

公开(公告)日：2016-08-09

申请号：US14473220

申请日：2014-08-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: G03F7/26 ,  H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/26 ,  H01L21/0337 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的基板上依次形成目标层和硬掩模层。 在第一区域的硬掩模层上以间隔物的形式形成转印图案。 光致抗蚀剂层直接形成在硬掩模层上，并且覆盖第一区域和第二区域中的转印图案和硬掩模层。 去除第一区域中的光致抗蚀剂层。 通过使用转印图案作为掩模来对硬掩模层进行图案化。