公开(公告)号：US20190067246A1

公开(公告)日：2019-02-28

申请号：US15683850

申请日：2017-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Chu-Yung Liu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.

公开(公告)号：US20180158950A1

公开(公告)日：2018-06-07

申请号：US15371293

申请日：2016-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  Chu-Yung Liu ,  I-Chen Yang ,  Hsin-Wen Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L27/112

CPC classification number: H01L29/7838 ,  H01L27/11286 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

公开(公告)号：US20160241021A1

公开(公告)日：2016-08-18

申请号：US14624409

申请日：2015-02-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Chieh-Wei He ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge protection device that includes a plurality of voltage drop elements, an impedance element, a driving circuit, and a clamping circuit is provided. The voltage drop elements are electrically connected in series between a first line and a node, and the voltage drop elements are configured to define an activating voltage. If a signal from the first line is greater than the activating voltage, the voltage drop elements conduct the first line to the node in response to the signal from the first line. The impedance element is electrically connected between the node and a second line. The driving circuit amplifies a control signal from the node and accordingly generates a driving signal. The clamping circuit determines whether to generate a discharging path between the first line and the second line according to the driving signal.

Abstract translation: 提供了包括多个电压降元件，阻抗元件，驱动电路和钳位电路的静电放电保护器件。 电压降元件在第一线路和节点之间串联电连接，并且电压降元件被配置为限定激活电压。 如果来自第一行的信号大于激活电压，则电压降元件响应于来自第一行的信号将第一行传导到节点。 阻抗元件电连接在节点和第二线之间。 驱动电路放大来自节点的控制信号，从而产生驱动信号。 钳位电路根据驱动信号确定是否在第一线路与第二线路之间产生放电路径。

公开(公告)号：US09208892B2

公开(公告)日：2015-12-08

申请号：US13943691

申请日：2013-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。

公开(公告)号：US20140092504A1

公开(公告)日：2014-04-03

申请号：US13573738

申请日：2012-10-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H02H9/04

CPC classification number: H02H9/044 ,  H01L27/0262 ,  H02H9/046

Abstract: An electrostatic discharge protection device including a silicon-controlled rectifier and a path switching circuit is provided. The silicon-controlled rectifier includes a first connection terminal, a second connection terminal, a first control terminal and a second control terminal, wherein the first connection terminal and the second connection terminal are respectively connected to a first line and a second line. The path switching circuit is electrically connected to the first line, the first control terminal and the second control terminal. When an input signal is supplied to the first line, the path switching circuit provides a first current path from the first line to the first control terminal in response to the input signal. When an electrostatic pulse is appeared on the first line, the path switching circuit provides a second current path from the first control terminal to the second control terminal in response to the electrostatic pulse.

Abstract translation: 提供一种包括硅控整流器和路径切换电路的静电放电保护装置。 硅控整流器包括第一连接端子，第二连接端子，第一控制端子和第二控制端子，其中第一连接端子和第二连接端子分别连接到第一线路和第二线路。 路径切换电路与第一线路，第一控制端子和第二控制端子电连接。 当输入信号被提供给第一行时，路径切换电路响应于输入信号提供从第一行到第一控制终端的第一电流路径。 当在第一线路上出现静电脉冲时，路径切换电路响应于静电脉冲提供从第一控制端子到第二控制端子的第二电流路径。

公开(公告)号：US20240243180A1

公开(公告)日：2024-07-18

申请号：US18153368

申请日：2023-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： I-Chen Yang ,  Chun Liang Lu ,  Yung-Hsiang Chen ,  Yao-Wen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/66598

Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

公开(公告)号：US20200265896A1

公开(公告)日：2020-08-20

申请号：US16277877

申请日：2019-02-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.

公开(公告)号：US10741250B1

公开(公告)日：2020-08-11

申请号：US16431913

申请日：2019-06-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chi-Yuan Chin

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/34 ,  G11C16/04

Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.

公开(公告)号：US09625520B2

公开(公告)日：2017-04-18

申请号：US14792148

申请日：2015-07-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G01R31/00 ,  G01R31/28 ,  G01R1/04

CPC classification number: G01R31/2853 ,  G01R1/0491 ,  G01R31/3004

Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.

公开(公告)号：US09466375B1

公开(公告)日：2016-10-11

申请号：US14724605

申请日：2015-05-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Che-Shih Lin ,  Yao-Wen Chang

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

Abstract: A memory device and a programming method thereof are provided, and the programming method for the memory device includes following steps. During a first period, a first voltage from a common source line is transmitted to first ends of a first memory cell string and a second memory cell string, and second ends of the first and the second memory cell strings are floated. During a second period, the first ends of the first and the second memory cell strings are floated, a second voltage and a third voltage are respectively transmitted to the second ends of the first and the second memory cell strings, and a programming voltage and a plurality of passing voltages are applied, so as to inhibit programming of the first memory cell string and sequentially program a plurality of memory cells in the second memory cell string from a second side of a memory array.

Abstract translation: 提供了存储器件及其编程方法，并且存储器件的编程方法包括以下步骤。 在第一时段期间，将来自公共源极线的第一电压发送到第一存储单元串和第二存储单元串的第一端，并且第一和第二存储单元串的第二端浮置。 在第二时段期间，第一和第二存储单元串的第一端被浮置，第二电压和第三电压分别被发送到第一和第二存储单元串的第二端，编程电压和 施加多个通过电压，以便禁止第一存储单元串的编程，并且从存储器阵列的第二侧顺序编程第二存储单元串中的多个存储单元。