公开(公告)号：US20100246255A1

公开(公告)日：2010-09-30

申请号：US12729626

申请日：2010-03-23

申请人： Yasuhiro SHIINO ,  Atsuhiro Sato ,  Takeshi Kamigaichi

发明人： Yasuhiro SHIINO ,  Atsuhiro Sato ,  Takeshi Kamigaichi

IPC分类号： G11C16/28

CPC分类号： G11C16/30 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  H01L27/11519 ,  H01L27/11521

摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.

摘要翻译： 非易失性半导体存储装置包括存储单元阵列和外围电路。 存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域 单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。 外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用 向第二接触器施加第三电压以改变虚设电池的阈值。

公开(公告)号：US07494869B2

公开(公告)日：2009-02-24

申请号：US11338707

申请日：2006-01-25

申请人： Atsuhiro Sato

发明人： Atsuhiro Sato

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C11/5621 ,  G11C16/0483 ,  H01L21/76232 ,  H01L27/11521 ,  H01L27/11524

摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.

摘要翻译： 公开了一种半导体集成电路器件的制造方法。 在半导体衬底上形成栅极绝缘膜。 在栅极绝缘膜上形成用作浮栅的第一膜。 通过第一膜在基板中形成沟槽。 绝缘材料嵌入沟槽中。 绝缘材料至少在平面方向回缩。 在绝缘材料的侧壁之间形成用作浮栅的第二膜，而不与绝缘材料的侧壁直接接触。 绝缘材料从绝缘材料和第二薄膜之间的空间回放。

公开(公告)号：US20060258092A1

公开(公告)日：2006-11-16

申请号：US11338707

申请日：2006-01-25

申请人： Atsuhiro Sato

发明人： Atsuhiro Sato

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28273 ,  G11C11/5621 ,  G11C16/0483 ,  H01L21/76232 ,  H01L27/11521 ,  H01L27/11524

摘要： A manufacturing method of a semiconductor integrated circuit device is disclosed. A gate insulating film is formed on a semiconductor substrate. A first film used as floating gates is formed on the gate insulating film. Trenches are formed in the substrate through the first film. Insulating materials are embedded in the trenches. The insulating materials are set back at least in a plane direction. Second films used as floating gates are formed between the side walls of the insulating materials without making directly contact with the side walls of the insulating materials. The insulating materials are set back from spaces caused between the insulating materials and the second films.

公开(公告)号：US07045423B2

公开(公告)日：2006-05-16

申请号：US11020314

申请日：2004-12-27

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

公开(公告)号：US20060033151A1

公开(公告)日：2006-02-16

申请号：US11259142

申请日：2005-10-27

申请人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

发明人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11536

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

公开(公告)号：US06977409B2

公开(公告)日：2005-12-20

申请号：US10685599

申请日：2003-10-16

申请人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

发明人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11536

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

公开(公告)号：US20050104120A1

公开(公告)日：2005-05-19

申请号：US11020314

申请日：2004-12-27

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/15 ,  H01L21/82

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

公开(公告)号：US20050094431A1

公开(公告)日：2005-05-05

申请号：US10948295

申请日：2004-09-24

申请人： Atsuhiro Sato ,  Riichiro Shirota ,  Kikuko Sugimae ,  Koji Sakui

发明人： Atsuhiro Sato ,  Riichiro Shirota ,  Kikuko Sugimae ,  Koji Sakui

IPC分类号： G11C16/06 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

CPC分类号： G11C16/06 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11546

摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.

摘要翻译： 非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。 控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

公开(公告)号：US20050003619A1

公开(公告)日：2005-01-06

申请号：US10717719

申请日：2003-11-21

申请人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Atsuhiro Sato ,  Hiroki Yamashita ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

摘要翻译： 半导体存储器包括存储单元矩阵，其包括沿列方向延伸的器件隔离膜，交替地布置在单元列之间; 第一导电层的顶表面低于器件隔离膜; 布置在相应的第一导电层上的电极间电介质，所述电极间电介质的介电常数大于氧化硅的介电常数; 和沿着行方向延伸的第二导电层，每个第二导电层布置在电极间电介质和器件隔离膜上，使得第二导电层可以被沿着行方向归属布置的存储单元晶体管共享 到不同的细胞柱。

公开(公告)号：US08541829B2

公开(公告)日：2013-09-24

申请号：US13235948

申请日：2011-09-19

申请人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

发明人： Kikuko Sugimae ,  Masayuki Ichige ,  Fumitaka Arai ,  Yasuhiko Matsunaga ,  Atsuhiro Sato

IPC分类号： H01L29/76 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.

摘要翻译： 非易失性半导体存储器包括：存储单元晶体管，包括形成在第一隧穿绝缘膜上的第一浮栅电极层，第一栅间绝缘膜，第一和第二控制栅极电极层以及第一金属硅化物膜; 包括形成在高压栅极绝缘膜上的高电压栅极电极层，具有孔径的第二栅极间绝缘膜，第三和第四控制栅极电极层以及第二金属硅化物膜的高压晶体管; 包括形成在第二隧道绝缘膜上的第二浮栅电极层，具有孔的第三栅间绝缘膜，第五和第六控制栅电极层和第三金属硅化物膜的低压晶体管; 以及直接设置在每个存储单元晶体管，低压晶体管和高压晶体管的源极和漏极区域上的衬垫绝缘膜。