公开(公告)号：US20080146043A1

公开(公告)日：2008-06-19

申请号：US11610758

申请日：2006-12-14

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

IPC分类号： H01L21/00

CPC分类号： H01L21/3105 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7846

摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

摘要翻译： 本发明提供一种制造半导体器件的方法。 用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层 的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

公开(公告)号：US20080145991A1

公开(公告)日：2008-06-19

申请号：US11641578

申请日：2006-12-19

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07199020B2

公开(公告)日：2007-04-03

申请号：US11103104

申请日：2005-04-11

申请人： Manoj Mehrotra ,  Hiroaki Niimi

发明人： Manoj Mehrotra ,  Hiroaki Niimi

IPC分类号： H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/76224

摘要： A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

摘要翻译： 公开了一种形成包括隔离结构的半导体器件的方法（1300），并且包括在半导体本体（1308）内形成沟槽区域。 然后，通过氮化处理将沟槽区域的表面氮化（1310）。 进行与氮化表面（1312）结合以形成含氮衬里的氧化工艺。 随后，沟槽区域填充有电介质材料（1316），然后平坦化（1318）以除去多余的电介质填充材料。

公开(公告)号：US20060189048A1

公开(公告)日：2006-08-24

申请号：US11060841

申请日：2005-02-18

申请人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

发明人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

IPC分类号： H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

摘要翻译： 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上形成封端的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

公开(公告)号：US06686300B2

公开(公告)日：2004-02-03

申请号：US10055262

申请日：2001-10-25

申请人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

发明人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

IPC分类号： H01L21302

CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

摘要： A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

公开(公告)号：US5493134A

公开(公告)日：1996-02-20

申请号：US338392

申请日：1994-11-14

申请人： Manoj Mehrotra ,  Bantval J. Baliga

发明人： Manoj Mehrotra ,  Bantval J. Baliga

IPC分类号： H01L29/739 ,  H01L29/745 ,  H01L29/747 ,  H01L29/749 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7397 ,  H01L29/747 ,  H01L29/749

摘要： A bidirectional semiconductor switching device includes a semiconductor substrate having first and second device terminals on opposite faces thereof, a thyristor in the substrate for providing regenerative conduction in a first direction, between the first device terminal and the second device terminal, and an insulated-gate bipolar junction transistor (IGBT) in the substrate for providing nonregenerative conduction in a second opposite direction, between the second device terminal and the first device terminal. In particular, the switching device includes first and second adjacent trenches therein at a face and respective first and second insulated-gate field effect transistors (IGFETs) in the trenches for providing gate-controlled turn-on and turn-off of the thyristor and the IGBT, by being electrically connected in series therewith.

摘要翻译： 一种双向半导体开关器件，包括：在其相对面上具有第一和第二器件端子的半导体衬底，用于在第一器件端子和第二器件端子之间的第一方向上提供再生传导的衬底中的晶闸管，以及绝缘栅极 在第二器件端子和第一器件端子之间在第二相反方向提供非再生导通的衬底中的双极结型晶体管（IGBT）。 特别地，开关器件包括位于其中的第一和第二相邻沟槽以及沟槽中的相应的第一和第二绝缘栅场效应晶体管（IGFET），用于提供栅极控制的晶闸管的导通和截止，以及 IGBT通过与其串联电连接。

公开(公告)号：US08691661B2

公开(公告)日：2014-04-08

申请号：US13284241

申请日：2011-10-28

申请人： Manoj Mehrotra

发明人： Manoj Mehrotra

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/3086 ,  H01L21/76232

摘要： An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion.

摘要翻译： 半导体器件的衬底中的隔离沟槽包括第一浅部，过渡区和第二较深部。 隔离沟槽包含介电填料。 隔离沟槽通过首先形成隔离沟槽的第一浅部，在第一浅部上形成多晶硅侧壁，然后蚀刻第二较深部分而形成。

公开(公告)号：US08685831B2

公开(公告)日：2014-04-01

申请号：US13284181

申请日：2011-10-28

申请人： Manoj Mehrotra

发明人： Manoj Mehrotra

IPC分类号： H01L21/76

CPC分类号： H01L21/3083 ,  H01L21/76232

摘要： An isolation trench in a substrate of a semiconductor device includes a first shallow portion with a dielectric sidewall and a second deeper portion without a dielectric sidewall. The isolation trench is formed by forming a first shallow portion of the trench, forming dielectric sidewalls on the first shallow portion, and then etching the substrate below the first shallow portion to form the second deeper portion. Shallow isolation trenches may be formed simultaneously with the etching of the second deeper portion.

摘要翻译： 半导体器件的衬底中的隔离沟槽包括具有电介质侧壁的第一浅部和没有电介质侧壁的第二较深部。 通过形成沟槽的第一浅部形成隔离沟槽，在第一浅部上形成电介质侧壁，然后在第一浅部下方蚀刻衬底以形成第二较深部分。 可以与第二较深部分的蚀刻同时形成浅的隔离沟槽。

公开(公告)号：US07960238B2

公开(公告)日：2011-06-14

申请号：US12344843

申请日：2008-12-29

申请人： Puneet Kohli ,  Manoj Mehrotra

发明人： Puneet Kohli ,  Manoj Mehrotra

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/823412 ,  H01L29/1083 ,  H01L29/66507 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm−3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface. A method to form an IC including at least one NMOS transistor includes implanting a first In implant at a first energy and a second In implant at a second energy, wherein the first In implant together with the second In implant form an In region having a retrograde profile under at least a portion of the channel region, and wherein the second energy is at least 5 keV more than the first energy.

摘要翻译： 集成电路（IC）包括至少一个NMOS晶体管，其中NMOS晶体管包括具有半导体表面的衬底，以及形成在栅极电介质上的包括栅电极的表面中或其上的栅堆叠，其中沟道区域位于 在栅极电介质下方的半导体表面。 源极和漏极区域在栅极堆叠的相对侧上。 具有逆行轮廓的An In区域在通道区域的至少一部分的下方。 逆行曲线包括（i）与栅极电介质的半导体表面界面处的表面In浓度小于5×10 16 cm -3，（ii）从栅极电介质下方的半导体表面至少20nm的峰In浓度， 并且其中（iii）峰In浓度比半导体表面界面处的In浓度高至少两（2）个数量级。 一种形成包括至少一个NMOS晶体管的IC的方法，包括以第二能量以第一能量和第二In的植入物注入第一InNo，其中第一In植入物与第二In植入物一起形成具有逆行的In区域 在所述通道区域的至少一部分下形成，并且其中所述第二能量比所述第一能量多至少5keV。

公开(公告)号：US07691700B2

公开(公告)日：2010-04-06

申请号：US11769058

申请日：2007-06-27

申请人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

发明人： Manoj Mehrotra ,  Stan Ashburn ,  Shaoping Tang

IPC分类号： H01L21/8238

CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1083 ,  H01L29/7833

摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.

摘要翻译： 本发明人的概念的一个方面涉及形成半导体器件的方法。 在该方法中，在半导体本体上形成栅极结构。 源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。 在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。 还公开了其它方法和装置。