公开(公告)号：US20180294407A1

公开(公告)日：2018-10-11

申请号：US16007079

申请日：2018-06-13

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Sonu Daryanani

IPC: H01L45/00

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

公开(公告)号：US20160380192A1

公开(公告)日：2016-12-29

申请号：US15262923

申请日：2016-09-12

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Sonu Daryanani

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1675

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract translation: 侧壁型存储单元（例如，CBRAM，ReRAM或PCM单元）可以包括底部电极，限定侧壁的顶部电极层和布置在底部和顶部电极层之间的电解质层，使得导电路径 经由电解质层限定在底部电极和顶部电极侧壁之间，其中底部电极层相对于水平衬底大致水平地延伸，并且顶部电极侧壁相对于水平衬底非水平地延伸，使得 当向单元施加正偏置电压时，导电路径在底电极和顶电极侧壁之间的非垂直方向（例如大致水平方向或其它非垂直方向）上生长。

公开(公告)号：US20160093632A1

公开(公告)日：2016-03-31

申请号：US14964548

申请日：2015-12-09

Applicant: Microchip Technology Incorporated

Inventor： Bomy Chen ,  Sonu Daryanani

IPC: H01L27/115 ,  H01L29/10 ,  H01L29/40 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/7816 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/2652 ,  H01L21/266 ,  H01L23/552 ,  H01L27/11524 ,  H01L27/11543 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7801 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract translation: 形成集成的DMOS晶体管/ EEPROM单元的方法包括在衬底上形成第一掩模，使用第一掩模在衬底中形成漂移注入以对准漂移注入，同时在漂移注入上形成第一浮栅，以及 与所述漂移注入件间隔开的第二浮动栅极，形成覆盖所述第二浮动栅极并覆盖所述第一浮动栅极的一部分的第二掩模，使用所述第一浮动栅极的边缘在所述基板中形成基底注入以使所述基底 并且同时在第一浮动栅极上形成第一控制栅极，并且在第二浮栅上方形成第二控制栅极。 第一浮栅，第一控制栅，漂移注入和基极注入形成DMOS晶体管的组件，第二浮栅和第二控制栅形成EEPROM单元的组件。

公开(公告)号：US20240282723A1

公开(公告)日：2024-08-22

申请号：US18351591

申请日：2023-07-13

Applicant: Microchip Technology Incorporated

Inventor： Matthew Martin ,  Bomy Chen ,  Julius Kovats

IPC: H01L23/64 ,  H01L21/3105 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/645 ,  H01L21/3105 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/24 ,  H01L25/16 ,  H01L2224/08235 ,  H01L2224/24226 ,  H01L2924/1206

Abstract: An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region including conductive routing structure and an inductor. The conductive routing structure is conductively connected to the bare die, and includes conductive elements formed in multiple conductive routing layers in the conductive routing region. The inductive device includes a winding formed in at least one conductive routing layer of the multiple conductive routing layers.

公开(公告)号：US20230290765A1

公开(公告)日：2023-09-14

申请号：US18064971

申请日：2022-12-13

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Julius Kovats ,  Anu Ramamurthy

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L25/0652 ,  H01L23/49811 ,  H01L24/40 ,  H01L24/16 ,  H01L24/73 ,  H01L24/48 ,  H01L24/37 ,  H01L24/84 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/37147 ,  H01L2224/40235 ,  H01L2224/48245 ,  H01L2224/73255 ,  H01L2224/40105 ,  H01L2224/40137 ,  H01L2224/40499 ,  H01L2924/0105 ,  H01L2224/84201 ,  H01L2224/95 ,  H01L2224/84007 ,  H01L23/49827 ,  H01L23/481

Abstract: An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.

公开(公告)号：US20230143437A1

公开(公告)日：2023-05-11

申请号：US17678655

申请日：2022-02-23

Applicant: Microchip Technology Incorporated

Inventor： Robert Lutwak ,  Bomy Chen

IPC: H03L7/26

CPC classification number: H03L7/26

Abstract: Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.

公开(公告)号：US10700171B2

公开(公告)日：2020-06-30

申请号：US15887088

申请日：2018-02-02

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Mel Hymas

IPC: H01L21/28 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.

公开(公告)号：US10546947B2

公开(公告)日：2020-01-28

申请号：US16110330

申请日：2018-08-23

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

公开(公告)号：US20180233371A1

公开(公告)日：2018-08-16

申请号：US15887088

申请日：2018-02-02

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Bomy Chen ,  Mel Hymas

IPC: H01L21/28 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/423

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-poly layer; and patterning and etching the second polysilicon layer to separate the second polysilicon layer into word line devices and erase gates.

公开(公告)号：US09601615B2

公开(公告)日：2017-03-21

申请号：US14964548

申请日：2015-12-09

Applicant: Microchip Technology Incorporated

Inventor： Bomy Chen ,  Sonu Daryanani

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/552 ,  H01L29/08 ,  H01L29/10 ,  H01L27/115 ,  H01L29/06 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L29/788 ,  G11C16/04 ,  G11C16/06

CPC classification number: H01L29/7816 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/2652 ,  H01L21/266 ,  H01L23/552 ,  H01L27/11524 ,  H01L27/11543 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7801 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.