公开(公告)号：US20200013669A1

公开(公告)日：2020-01-09

申请号：US16577012

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/744 ,  H01L21/308 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8239 ,  H01L27/102 ,  H01L29/749 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/423

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US10510957B2

公开(公告)日：2019-12-17

申请号：US15660829

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

公开(公告)号：US20190295642A1

公开(公告)日：2019-09-26

申请号：US16372010

申请日：2019-04-01

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

IPC: G11C13/00

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

公开(公告)号：US10276235B2

公开(公告)日：2019-04-30

申请号：US15980480

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

IPC: G11C13/00 ,  G11C7/04

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

公开(公告)号：US20180268899A1

公开(公告)日：2018-09-20

申请号：US15980480

申请日：2018-05-15

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

IPC: G11C13/00 ,  G11C7/04

CPC classification number: G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

公开(公告)号：US20170236744A1

公开(公告)日：2017-08-17

申请号：US15584413

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Marcello D. Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L21/762 ,  H01L29/423 ,  H01L27/102 ,  H01L29/66 ,  H01L29/78 ,  H01L27/105 ,  H01L21/8234 ,  H01L21/8229

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/8239 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/744 ,  H01L29/749 ,  H01L29/7827

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

公开(公告)号：US20160049404A1

公开(公告)日：2016-02-18

申请号：US14461751

申请日：2014-08-18

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Anna Maria Conti ,  Sara Vigano

IPC: H01L27/105 ,  H01L27/102 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8222 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L27/088 ,  H01L29/744

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/8229 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/8239 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/744 ,  H01L29/749 ,  H01L29/7827

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Abstract translation: 门阵列阵列包括排列成行和列的多个选通装置，并且分别包括正面内部区域，内部区域的正上方的中间区域和中部区域的高度外侧区域。 多个接入线沿着行的单独侧向靠近中间区域。 多条数据/感测线分别在接入线的外侧朝向外侧，并且沿着各列的电极电耦合到外部区域。 多个金属线分别在接近线的垂直方向上沿着并且紧邻行的紧邻之间延伸。 各个金属线直接抵靠和电耦合到紧邻行中的每一个的内部区域的侧壁。 金属线与数据/感测线电隔离。 公开了门控器件的其它阵列和形成门控器件阵列的方法。

公开(公告)号：US12082424B2

公开(公告)日：2024-09-03

申请号：US17671373

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Anna Maria Conti

IPC: H01L27/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11514 ,  H01L45/00 ,  H10B53/20 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/32133 ,  H01L21/76837 ,  H01L21/76892 ,  H01L23/528 ,  H10B53/20 ,  H10B63/24 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8825

Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

公开(公告)号：US20240029794A1

公开(公告)日：2024-01-25

申请号：US17868118

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Anna Maria Conti ,  Harsh Narendrakumar Jain ,  H. Montgomery Manning

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230326867A1

公开(公告)日：2023-10-12

申请号：US17715481

申请日：2022-04-07

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Raj K. Bansal

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L23/562 ,  H01L2225/06562 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2225/06506 ,  H01L21/78

Abstract: Methods, systems, and devices for techniques for forming a device with scribe asymmetry are described. Circuits (e.g., arrays of memory cells) may be printed on a wafer and separated by scribes of various widths to increase an array efficiency of a fabrication process. For example, a scribe that extends in a first direction may have a width in a second direction. A first subset of scribes may have a first width, where one or more structures may be placed in the first subset of scribes to facilitate die testing and integration. A second subset of scribes may have a second width. In some examples, the structures may not be placed in the second subset of scribes and, accordingly, the second width may be less than the first width.