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公开(公告)号：US20170256319A1
公开(公告)日：2017-09-07
申请号：US15598103
申请日：2017-05-17
Applicant: Micron Technology, Inc.
Inventor： Daniele Balluchi , Corrado Villa
CPC classification number: G11C16/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3436 , G11C16/3459 , G11C2213/79
Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.
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公开(公告)号：US09454310B2
公开(公告)日：2016-09-27
申请号：US14181089
申请日：2014-02-14
Applicant: Micron Technology, Inc.
Inventor： Victor Y. Tsai , Danilo Caraccio , Daniele Balluchi , Neal A. Galbo , Robert Warren
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0611 , G06F3/0679 , G06F3/0688
Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
Abstract translation: 本公开包括用于命令排队的装置和方法。 许多实施例包括从主机在存储器系统处接收排队的命令请求，从存储器系统向主机发送指示存储器系统准备好在存储器系统的命令队列中接收命令的命令响应，以及 响应于发送命令响应，从所述主机接收在所述存储器系统处的所述命令的命令描述符块。
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公开(公告)号：US20250094344A1
公开(公告)日：2025-03-20
申请号：US18782380
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Rishabh Dubey , Marco Sforzin , Emanuele Confalonieri , Danilo Caraccio , Daniele Balluchi , Nicola Del Gatto
Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20250069680A1
公开(公告)日：2025-02-27
申请号：US18949086
申请日：2024-11-15
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Antonino Caprì , Daniele Balluchi , Massimiliano Patriarca
IPC: G11C29/52 , G11C11/406 , G11C11/4093
Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.
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公开(公告)号：US20250028486A1
公开(公告)日：2025-01-23
申请号：US18803440
申请日：2024-08-13
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Paolo Amato , Daniele Balluchi
IPC: G06F3/06
Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.
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Patent Agency Ranking
公开(公告)号：US12189478B2
公开(公告)日：2025-01-07
申请号：US17828475
申请日：2022-05-31
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Daniele Balluchi
IPC: G06F11/10
Abstract: A system and method for memory error recovery in compute express link (CXL) components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
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公开(公告)号：US12148498B2
公开(公告)日：2024-11-19
申请号：US17959191
申请日：2022-10-03
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Antonino Caprì , Daniele Balluchi , Massimiliano Patriarca
IPC: G11C11/406 , G11C11/4093 , G11C29/52
Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.
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公开(公告)号：US12100438B2
公开(公告)日：2024-09-24
申请号：US17404487
申请日：2021-08-17
Applicant: Micron Technology, Inc.
Inventor： Dionisio Minopoli , Marco Sforzin , Daniele Balluchi
IPC: G11C7/04 , G11C11/406 , G11C11/4076
CPC classification number: G11C11/40626 , G11C11/40615 , G11C11/40622 , G11C11/4076
Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.
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公开(公告)号：US20240296094A1
公开(公告)日：2024-09-05
申请号：US18660954
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin , Daniele Balluchi
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/1004
Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity can be used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).
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公开(公告)号：US12079509B2
公开(公告)日：2024-09-03
申请号：US17868286
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Daniele Balluchi , Paolo Amato , Danilo Caraccio , Marco Sforzin
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F11/1048
Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.
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