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    Semiconductor packages with indications of die-specific information
    33.
    发明授权
    Semiconductor packages with indications of die-specific information 有权

    公开(公告)号：US11532490B2

    公开(公告)日：2022-12-20

    申请号：US16548084

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/00 ,  H01L23/544 ,  H01L21/67

    Abstract: Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.

    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
    34.
    发明申请
    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES 有权

    公开(公告)号：US20220208262A1

    公开(公告)日：2022-06-30

    申请号：US17697567

    申请日：2022-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

    IPC: G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

    Systems and techniques for accessing multiple memory cells concurrently
    35.
    发明授权
    Systems and techniques for accessing multiple memory cells concurrently 有权

    公开(公告)号：US11335402B2

    公开(公告)日：2022-05-17

    申请号：US16712682

    申请日：2019-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G11C13/00

    Abstract: Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
    36.
    发明申请
    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES 审中-公开

    公开(公告)号：US20200294586A1

    公开(公告)日：2020-09-17

    申请号：US16791764

    申请日：2020-02-14

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

    Auto-referenced memory cell read techniques
    37.
    发明授权
    Auto-referenced memory cell read techniques 有权

    公开(公告)号：US10600480B2

    公开(公告)日：2020-03-24

    申请号：US16536120

    申请日：2019-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

    IPC: G11C7/10 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
    38.
    发明申请
    AUTO-REFERENCED MEMORY CELL READ TECHNIQUES 审中-公开

    公开(公告)号：US20190198099A1

    公开(公告)日：2019-06-27

    申请号：US15853364

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Paolo Amato ,  Federico Pio ,  Alessandro Orlando ,  Marco Sforzin

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0054 ,  H01L27/2481 ,  H01L45/06

    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

    Three dimensional memory array architecture
    40.
    发明授权
    Three dimensional memory array architecture 有权
    三维内存阵列架构

    公开(公告)号：US09444046B2

    公开(公告)日：2016-09-13

    申请号：US14268649

    申请日：2014-05-02

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: H01L45/00 ,  G11C11/00 ,  H01L47/00 ,  H01L21/283 ,  H01L29/82 ,  H01L27/10 ,  H01L27/24 ,  H01L29/417 ,  H01L29/78 ,  H01L27/06

    CPC classification number: H01L45/16 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/249 ,  H01L29/41758 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

    Abstract translation: 提供三维存储器阵列结构及其形成方法。 示例性存储器阵列可以包括堆叠，其包括通过至少绝缘材料彼此分开的多个级别的多个第一导电线，以及布置成基本上垂直于多个第一导电线延伸的至少一个导电延伸部。 存储元件材料围绕至少一个导电延伸部形成。 细胞选择材料形成在至少一个导电延伸部周围。 所述至少一个导电延伸部，存储元件材料和电池选择材料位于所述多个第一导电线的共面对之间。

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