公开(公告)号：US10170491B2

公开(公告)日：2019-01-01

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11524

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US09991273B2

公开(公告)日：2018-06-05

申请号：US15691477

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/1156 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US20170133392A1

公开(公告)日：2017-05-11

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US09397210B2

公开(公告)日：2016-07-19

申请号：US14043943

申请日：2013-10-02

Applicant: Micron Technology, Inc.

Inventor： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/764

CPC classification number: H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.

Abstract translation: 存储器阵列具有半导体上的第一和第二存储器单元以及延伸到半导体中的隔离区。 隔离区包括第一和第二存储单元的电荷存储结构之间的气隙和气隙上的电介质的厚度，并且包含在第一和第二存储单元之间。

公开(公告)号：US20150123189A1

公开(公告)日：2015-05-07

申请号：US14069574

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

公开(公告)号：US20250111346A1

公开(公告)日：2025-04-03

申请号：US18775071

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Mohad Baboli ,  John Hopkins

IPC: G06Q20/10 ,  G06Q10/02 ,  G06Q10/0639 ,  G06Q30/0283 ,  G06Q50/47 ,  G06V20/59 ,  G06V40/20 ,  H04L43/0876 ,  H04L67/50

Abstract: A system and method for determining a ride fare for a ride in a network-connected autonomous vehicle is disclosed. The system may divide an overall ride fare between the rider, and the enterprise or company at which the rider is employed, where the amounts allocated to each are dependent upon a productivity metric indicating a measure of the work performed by the rider during the ride. Accordingly, the system receives a ride request over a network and calculates an overall ride fare using ride parameters. At the ride's conclusion, the system receives a productivity metric indicating rider productivity enabled by the vehicle's virtual work environment. The system uses the productivity metric to calculate a portion of the overall fare allocated to the rider's account. The virtual environment may include network connectivity, input devices, displays, and cloud-based productivity software. A productivity sensing system generates the productivity metric by monitoring network traffic, or monitoring software application interactions.

公开(公告)号：US20250071940A1

公开(公告)日：2025-02-27

申请号：US18773959

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee

IPC: H05K7/20 ,  H01L21/67

Abstract: Apparatus and methods are disclosed, including cooling devices and systems. Cooling devices and methods are shown that include dissolved ions in cooling fluid, such as cooling water. Cooling devices and methods are shown that include an electrical conductivity measurement sensor within the cooling water, wherein the electrical conductivity measurement sensor includes an electrode resistant to the dissolved ions.

公开(公告)号：US20230395704A1

公开(公告)日：2023-12-07

申请号：US17804997

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee

IPC: H01L29/66 ,  H01L27/1157 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L29/792 ,  H01L27/1157

Abstract: Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

公开(公告)号：US20230290739A1

公开(公告)日：2023-09-14

申请号：US17694040

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John Hopkins

IPC: H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/40114 ,  H01L29/40117 ,  H01L23/53257 ,  H01L23/5226 ,  H01L23/5283

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; a first pillar extending through the tiers and separated from the control gates, the first pillar including a first dielectric liner portion and a first core portion adjacent the first dielectric liner portion, the first dielectric liner portion and the first core portion extending along a length of the first pillar; and a second pillar extending through the tiers and separated from the control gates, the second pillar including a second dielectric liner portion and a second core portion adjacent the second dielectric liner portion, the second dielectric portion and the second core portion extending along a length of the second pillar, wherein the first core portion and the second core portion have different materials.

公开(公告)号：US11682581B2

公开(公告)日：2023-06-20

申请号：US17127823

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B43/27 ,  H10B41/27 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.