公开(公告)号：US20190206726A1

公开(公告)日：2019-07-04

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20160307839A1

公开(公告)日：2016-10-20

申请号：US15192060

申请日：2016-06-24

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

IPC: H01L23/528 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

Abstract translation: 形成半导体结构的方法包括在衬底结构中形成酸性或碱性材料的集合体。 在酸性或碱性材料和衬底结构的池之上形成抗蚀剂。 酸性或碱性材料从池中扩散到靠近池的抗蚀剂的部分，而不是远离池的抗蚀剂的部分。 然后，与远离池的抗蚀剂部分相比，抗蚀剂暴露于显影剂以除去更靠近池的抗蚀剂部分，以在抗蚀剂中形成开口。 开口具有靠近基板结构的较宽部分和远离基板结构的较窄部分。 该方法还可以包括在抗蚀剂的开口中形成特征。 这些特征具有靠近基底结构的较宽部分和远离基底结构的较窄部分。

公开(公告)号：US09396996B2

公开(公告)日：2016-07-19

申请号：US14848912

申请日：2015-09-09

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/768 ,  H01L21/467 ,  H01L23/52 ,  H01L21/027 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

Abstract translation: 形成半导体结构的方法包括在衬底结构中形成酸性或碱性材料的集合体。 在酸性或碱性材料和衬底结构的池之上形成抗蚀剂。 酸性或碱性材料从池中扩散到靠近池的抗蚀剂的部分，而不是远离池的抗蚀剂的部分。 然后，与远离池的抗蚀剂部分相比，抗蚀剂暴露于显影剂以除去更靠近池的抗蚀剂部分，以在抗蚀剂中形成开口。 开口具有靠近基板结构的较宽部分和远离基板结构的较窄部分。 该方法还可以包括在抗蚀剂的开口中形成特征。 这些特征具有靠近基底结构的较宽部分和远离基底结构的较窄部分。

公开(公告)号：US20150380307A1

公开(公告)日：2015-12-31

申请号：US14848912

申请日：2015-09-09

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

Abstract translation: 形成半导体结构的方法包括在衬底结构中形成酸性或碱性材料的集合体。 在酸性或碱性材料和衬底结构的池之上形成抗蚀剂。 酸性或碱性材料从池中扩散到靠近池的抗蚀剂的部分，而不是远离池的抗蚀剂的部分。 然后，与远离池的抗蚀剂部分相比，抗蚀剂暴露于显影剂以除去更靠近池的抗蚀剂部分，以在抗蚀剂中形成开口。 开口具有靠近基板结构的较宽部分和远离基板结构的较窄部分。 该方法还可以包括在抗蚀剂的开口中形成特征。 这些特征具有靠近基底结构的较宽部分和远离基底结构的较窄部分。

公开(公告)号：US09209039B2

公开(公告)日：2015-12-08

申请号：US14312945

申请日：2014-06-24

Applicant: Micron Technology, Inc.

Inventor： Kaveri Jain ,  Anton J. deVilliers

IPC: H01L21/308 ,  G03F7/20

CPC classification number: H01L21/3086 ,  G03F7/2022 ,  Y10T428/24802

Abstract: A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a first polarity. The polarity of the patterned resist is reversed to a second polarity, and a reversal film is formed over the patterned resist having the second polarity. The patterned resist having the second polarity is removed, forming a pattern in the reversal film. The pattern in the reversal film is then transferred to the substrate. Additional methods of forming a reversed pattern in a substrate are disclosed, as is a semiconductor structure formed during the methods.

Abstract translation: 在基板中形成反转图案的方法。 衬底上的抗蚀剂被曝光和显影以在其中形成图案，图案化抗蚀剂具有第一极性。 图案化抗蚀剂的极性反转到第二极性，并且在具有第二极性的图案化抗蚀剂上形成反转膜。 去除具有第二极性的图案化抗蚀剂，在反转膜中形成图案。 然后将反转膜中的图案转移到基底。 公开了在衬底中形成反向图案的附加方法，以及在该方法期间形成的半导体结构。

公开(公告)号：US09184058B2

公开(公告)日：2015-11-10

申请号：US14139582

申请日：2013-12-23

Applicant: Micron Technology, Inc. ,  Dow Global Technologies LLC ,  Rohm and Haas Electronic Materials LLC

Inventor： William R. Brown ,  Adam Olson ,  Kaveri Jain ,  Ho Seop Eom ,  Xue Gloria Chen ,  Nik Mirin ,  Dan Millward ,  Peter Trefonas, III ,  Phillip Dene Hustad ,  Jong Keun Park ,  Christopher Nam Lee

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/0274 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

Abstract: Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material.

Abstract translation: 一些实施例包括形成图案的方法。 在材料上形成第一个掩模。 第一掩模具有在其中延伸的特征并且限定第一图案。 第一种模式在特征分布上具有第一级的均匀性。 在第一掩模之间并且在特征内形成刷层以使特征变窄以从第一掩模创建第二掩模。 所述第二掩模具有比所述第一级别的均匀性更窄的所述窄化特征的第二级别的均匀性。 图案从第二个掩模转移到材料中。

公开(公告)号：US20140247476A1

公开(公告)日：2014-09-04

申请号：US14277323

申请日：2014-05-14

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jianming Zhou ,  Scott L. Light ,  Anton deVilliers ,  Kaveri Jain ,  Zishu Zhang ,  Dan Millward

IPC: G02B26/06

CPC classification number: G02B26/06 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/70258 ,  G03F7/70308 ,  G03F7/705 ,  G03F7/706

Abstract: Some embodiments include system and methods to obtain information for adjusting variations in features formed on a substrate of a semiconductor device. Such methods can include determining a first pupil in an illumination system used to form a first feature, and determining a second pupil used to form a second feature. The methods can also include determining a pupil portion belonging to only one of the pupils, and generating a modified pupil portion from the pupil portion. Information associated with the modified pupil portion can be obtained for controlling a portion of a projection lens assembly of an illumination system. Other embodiments are described.

Abstract translation: 一些实施例包括用于获得用于调整形成在半导体器件的衬底上的特征的变化的信息的系统和方法。 这样的方法可以包括确定用于形成第一特征的照明系统中的第一光瞳，以及确定用于形成第二特征的第二光瞳。 所述方法还可以包括确定属于仅一个瞳孔的瞳孔部分，并且从瞳孔部分产生修改的瞳孔部分。 可以获得与修改的瞳孔部分相关联的信息，用于控制照明系统的投影透镜组件的一部分。 描述其他实施例。

公开(公告)号：US08815497B2

公开(公告)日：2014-08-26

申请号：US13941747

申请日：2013-07-15

Applicant: Micron Technology, Inc.

Inventor： Dan Millward ,  Kaveri Jain ,  Zishu Zhang ,  Lijing Gou ,  Anton J. deVillers ,  Jianming Zhou ,  Yuan He ,  Michael Hyatt ,  Scott L. Light

IPC: G03F7/26

CPC classification number: H01L21/76879 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10888

Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Abstract translation: 一些实施例包括形成图案的方法。 半导体衬底被形成为在一组导电结构之上包括电绝缘材料。 跨导电结构限定互连区域，并且互连区域的相对侧上的区域被定义为次级区域。 特征的二维阵列形成在电绝缘材料上。 二维阵列跨越互连区域并跨越次级区域延伸。 二维阵列的图案通过互连区域的电绝缘材料转移以形成延伸穿过电绝缘材料和导电结构的接触开口，并且二次区域的二维阵列的任何部分 被转移到电绝缘材料中。