公开(公告)号：US20190287605A1

公开(公告)日：2019-09-19

申请号：US16431500

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4097

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US10163908B2

公开(公告)日：2018-12-25

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US20160155745A1

公开(公告)日：2016-06-02

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/66621 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US12004341B2

公开(公告)日：2024-06-04

申请号：US17886917

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Si-Woo Lee

IPC: H10B12/00

CPC classification number: H10B12/36 ,  H10B12/056 ,  H10B12/50

Abstract: A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

公开(公告)号：US20240172420A1

公开(公告)日：2024-05-23

申请号：US18428581

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H10B12/00 ,  G11C11/402 ,  H01L25/065 ,  H01L27/06

CPC classification number: H10B12/36 ,  G11C11/4023 ,  H01L25/0657 ,  H01L27/0688 ,  H10B12/056

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US20230240067A1

公开(公告)日：2023-07-27

申请号：US18131097

申请日：2023-04-05

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/50 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/02603 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/09 ,  H10B12/30

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US11631681B2

公开(公告)日：2023-04-18

申请号：US17189485

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US20220352171A1

公开(公告)日：2022-11-03

申请号：US17867628

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US20220293598A1

公开(公告)日：2022-09-15

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220108987A1

公开(公告)日：2022-04-07

申请号：US17060356

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim ,  Kyuseok Lee ,  Sangmin Hwang ,  Mark Zaleski

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10 ,  G11C5/02

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.