公开(公告)号：US10741636B2

公开(公告)日：2020-08-11

申请号：US16183463

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L49/02 ,  H01L21/3065 ,  H01L29/66

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

公开(公告)号：US20190273058A1

公开(公告)日：2019-09-05

申请号：US16414440

申请日：2019-05-16

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US20190074351A1

公开(公告)日：2019-03-07

申请号：US16183463

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu

IPC: H01L49/02

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

公开(公告)号：US10121849B2

公开(公告)日：2018-11-06

申请号：US14941665

申请日：2015-11-16

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L49/02 ,  H01L21/304 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L29/92 ,  C23C14/16 ,  C23C16/06 ,  C23C16/40 ,  C23C16/34 ,  C23C14/06 ,  C23C14/10 ,  C23C14/08 ,  H01L21/3065 ,  H01L23/48

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

公开(公告)号：US20180190761A1

公开(公告)日：2018-07-05

申请号：US15396828

申请日：2017-01-03

Applicant: Micron Technology, Inc.

Inventor： Hsu Chiang ,  Neng-Tai Shih ,  Tieh-Chiang Wu

IPC: H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/288 ,  H01L21/027

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A metal-insulator-metal (MIM) capacitor is disclosed. The MIM capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. The bottom electrode includes a metal plate and a three-dimensional (3D) metal structure protruding from a top surface of the metal plate. A second dielectric layer surrounds the 3D metal structure. A capacitor dielectric layer covers the 3D metal structure and the second dielectric layer. A top electrode is disposed on the capacitor dielectric layer. The top electrode has fins that interdigitate with the 3D metal structure.

公开(公告)号：US20170365580A1

公开(公告)日：2017-12-21

申请号：US15676350

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/81

Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die ant the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.

公开(公告)号：US09704790B1

公开(公告)日：2017-07-11

申请号：US15069911

申请日：2016-03-14

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L21/44 ,  H01L23/12 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/50 ,  H01L21/78 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2021/60255 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side, opposite to the first side. The RDL interposer comprises a first passivation layer, at least one dielectric layer on the first passivation layer, a metal layer in the at least one dielectric layer, a second passivation layer on the at least one dielectric layer, and a plurality of ball pads in the first passivation layer. At least one semiconductor die is mounted on the first side of the RDL interposer. A solder mask covers a lower surface of the first passivation layer and exposes the plurality of ball pads through a plurality of openings in the solder mask. An under-bump mettalization (UBM) layer is disposed at a bottom of each of the plurality of openings. A solder bump or solder ball is disposed on the UBM layer in each of the plurality of openings.