公开(公告)号：US20240349505A1

公开(公告)日：2024-10-17

申请号：US18615110

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Collin Howder

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers comprise a first silicon oxide. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conductive material of one of the conductive tiers. Individual of the treads comprise a second silicon oxide directly above the conductive material of the one conductive tier. The second silicon oxide comprises one or more of boron and phosphorus at a total concentration that is greater than a total concentration of one or more of boron and phosphorus, if any, that is in the first silicon oxide that is directly below the second silicon oxide. A conductive-via construction extends downwardly from and directly below the conductive material of the individual treads to circuitry that is directly below the stack. The conductive-via construction comprises conductor material that directly electrically couples together the conductive material of one of the individual treads and the circuitry that is directly below the stack. Methods are disclosed.

公开(公告)号：US20240258233A1

公开(公告)日：2024-08-01

申请号：US18420538

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Harsh Narendrakumar Jain

IPC: H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/76877 ,  H01L29/4011

Abstract: Methods, systems, and devices for staircase landing pads via rivets are described. A memory device may include a staircase region with a stack of materials that includes a set of word lines, where the set of word lines progressively decrease in length to form a staircase structure. The staircase region may additionally include a rivet that couples a first word line from the set of word lines with a conductive pillar. Additionally, the conductive pillar may traverse the stack perpendicularly to the set of word lines and may couple the first word line with supporting circuitry. In some cases, a first thickness of the first word line adjacent to the conductive pillar may be greater than a second thickness of other word lines adjacent to the conductive pillar. The staircase region may additionally include an oxide material that isolates the conductive pillar from the other word lines.

公开(公告)号：US20240074201A1

公开(公告)日：2024-02-29

申请号：US17893436

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Albert Fayrushin ,  Sidhartha Gupta ,  Jun Fujiki ,  Masashi Yoshida ,  Yiping Wang ,  Taehyun Kim ,  Arun Kumar Dhayalan

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230335500A1

公开(公告)日：2023-10-19

申请号：US18214911

申请日：2023-06-27

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US11729964B2

公开(公告)日：2023-08-15

申请号：US17449352

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Silvia Borsari ,  Stian E. Wood ,  Haoyu Li ,  Yiping Wang

IPC: H01L27/108 ,  H01L21/768 ,  H01L27/08 ,  H10B12/00

CPC classification number: H10B12/30 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/0814 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488 ,  H01L2221/1057

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

公开(公告)号：US11594495B2

公开(公告)日：2023-02-28

申请号：US17209993

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220262678A1

公开(公告)日：2022-08-18

申请号：US17736365

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jordan D. Greenlee ,  Collin Howder

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210358940A1

公开(公告)日：2021-11-18

申请号：US15931421

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/306 ,  H01L21/283

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210057428A1

公开(公告)日：2021-02-25

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US20200373304A1

公开(公告)日：2020-11-26

申请号：US16420429

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Silvia Borsari ,  Stian E. Wood ,  Haoyu Li ,  Yiping Wang

IPC: H01L27/108

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.