公开(公告)号：US09362274B2

公开(公告)日：2016-06-07

申请号：US13867684

申请日：2013-04-22

申请人： Eng Huat Toh ,  Elgin Quek

发明人： Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

公开(公告)号：US09064803B2

公开(公告)日：2015-06-23

申请号：US13189964

申请日：2011-07-25

申请人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/513

摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

摘要翻译： 分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。 实施例包括具有包含低k和高k层的电介质间隔物的存储单元。 其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

公开(公告)号：US08470700B2

公开(公告)日：2013-06-25

申请号：US12804487

申请日：2010-07-22

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

IPC分类号： H01L21/26

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

公开(公告)号：US20120292707A1

公开(公告)日：2012-11-22

申请号：US13108439

申请日：2011-05-16

申请人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

IPC分类号： H01L21/336 ,  H01L29/78 ,  B82Y99/00

CPC分类号： H01L29/685 ,  B81B3/0081 ,  B81B2203/0109 ,  B81B2207/015 ,  B82Y10/00 ,  G11C11/56 ,  G11C23/00 ,  G11C2213/16 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.

摘要翻译： 半导体器件由体积衬底上的纳米机电系统（NEMS）逻辑或存储器形成。 实施例包括直接在体基板上形成源极/漏极区域，形成连接源极/漏极区域的鳍片，形成两个栅极，鳍片的每一侧上一个，两个栅极与本体衬底绝缘，以及形成衬底栅极 在散装衬底中。 翅片与具有气隙的两个栅极和衬底栅极中的每一个分离。

公开(公告)号：US20120228705A1

公开(公告)日：2012-09-13

申请号：US13046332

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.

摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层， 第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。 其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

公开(公告)号：US20120228695A1

公开(公告)日：2012-09-13

申请号：US13046313

申请日：2011-03-11

申请人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US09029227B2

公开(公告)日：2015-05-12

申请号：US13038081

申请日：2011-03-01

申请人： Eng Huat Toh ,  Elgin Quek ,  Ying Keung Leung ,  Sanford Chu

发明人： Eng Huat Toh ,  Elgin Quek ,  Ying Keung Leung ,  Sanford Chu

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L27/06 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513

摘要： A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.

摘要翻译： 形成p沟道闪速存储器，其中嵌入有形成有升高的源极/漏极的异质结层中的电荷存储堆叠。 实施例包括在衬底上形成虚拟栅极堆叠，通过选择性外延生长在虚设栅极堆叠的每一侧上在衬底上形成层，在层上形成间隔物，形成升高的源极/漏极，去除虚拟栅极堆叠，形成 间隔件之间的空腔，并且在空腔中形成存储器栅极堆叠。 不同的实施例包括形成窄带隙材料的层，在间隔物下方的窄带隙层和与其相邻的宽带隙层，或在间隔物下方的宽带隙层，与其相邻的窄带隙层，以及宽带隙层 窄带隙层。

公开(公告)号：US08502279B2

公开(公告)日：2013-08-06

申请号：US13108439

申请日：2011-05-16

申请人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Chung Foong Tan

IPC分类号： H01L29/84 ,  H01L29/66 ,  H01L21/00 ,  H01L21/338 ,  H01L21/336

CPC分类号： H01L29/685 ,  B81B3/0081 ,  B81B2203/0109 ,  B81B2207/015 ,  B82Y10/00 ,  G11C11/56 ,  G11C23/00 ,  G11C2213/16 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.

摘要翻译： 半导体器件由体积衬底上的纳米机电系统（NEMS）逻辑或存储器形成。 实施例包括直接在体基板上形成源极/漏极区域，形成连接源极/漏极区域的鳍片，形成两个栅极，鳍片的每一侧上一个，两个栅极与本体衬底绝缘，以及形成衬底栅极 在散装衬底中。 翅片与具有气隙的两个栅极和衬底栅极中的每一个分离。

公开(公告)号：US20130026552A1

公开(公告)日：2013-01-31

申请号：US13189964

申请日：2011-07-25

申请人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/513

摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

公开(公告)号：US20120223318A1

公开(公告)日：2012-09-06

申请号：US13038081

申请日：2011-03-01

申请人： Eng Huat Toh ,  Elgin Quek ,  Ying Keung Leung ,  Sanford Chu

发明人： Eng Huat Toh ,  Elgin Quek ,  Ying Keung Leung ,  Sanford Chu

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513

摘要： A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.

摘要翻译： 形成p沟道闪速存储器，其中嵌入有形成有升高的源极/漏极的异质结层中的电荷存储堆叠。 实施例包括在衬底上形成虚拟栅极堆叠，通过选择性外延生长在虚设栅极堆叠的每一侧上在衬底上形成层，在层上形成间隔物，形成升高的源极/漏极，去除虚拟栅极堆叠，形成 间隔件之间的空腔，并且在空腔中形成存储器栅极堆叠。 不同的实施例包括形成窄带隙材料的层，在间隔物下方的窄带隙层和与其相邻的宽带隙层，或在间隔物下方的宽带隙层，与其相邻的窄带隙层，以及宽带隙层 窄带隙层。