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公开(公告)号：US20190298152A1
公开(公告)日：2019-10-03
申请号：US16445373
申请日：2019-06-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
Abstract: A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.
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公开(公告)号：US10297626B2
公开(公告)日：2019-05-21
申请号：US15794474
申请日：2017-10-26
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
Abstract: A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an nth layer, and signal lines of the first layer to the nth layer. n is an integer of two or more. The switch array of an ith layer is disposed between the switch array of an (i+1)th layer and the amplifier. i is an integer of one or more and less than n. The signal line of the first layer is connected to the nth amplifier. The signal line of the nth layer is connected to the switch array of the nth layer. Each of the plurality of switches included in the switch array of the nth layer is connected to the column circuit.
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公开(公告)号：US10277237B2
公开(公告)日：2019-04-30
申请号：US16043920
申请日：2018-07-24
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Hideki Kato
Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.
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Patent Agency Ranking
公开(公告)号：US20180351568A1
公开(公告)日：2018-12-06
申请号：US16100534
申请日：2018-08-10
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide , Yasunari Harada , Masato Osawa , Hideki Kato
IPC: H03M1/46 , H01G4/012 , H01G4/38 , H01L23/522
CPC classification number: H03M1/46 , H01G4/012 , H01G4/38 , H01G4/40 , H01L23/5223 , H01L23/5225 , H03M1/466
Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.
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公开(公告)号：US20180184026A1
公开(公告)日：2018-06-28
申请号：US15902014
申请日：2018-02-22
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
CPC classification number: H04N5/363 , H04N5/3575 , H04N5/365 , H04N5/378
Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.
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公开(公告)号：US20180102768A1
公开(公告)日：2018-04-12
申请号：US15837299
申请日：2017-12-11
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Masato Osawa , Hideki Kato
CPC classification number: H03K5/08 , H03F3/45 , H03F3/45188 , H03F3/45475 , H03F3/45659 , H03F2203/45288 , H03F2203/45424 , H03F2203/45514 , H03F2203/45551 , H03M1/1014 , H03M1/1061 , H03M1/468 , H04N5/374 , H04N5/378
Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.
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公开(公告)号：US20180047771A1
公开(公告)日：2018-02-15
申请号：US15794474
申请日：2017-10-26
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
CPC classification number: H01L27/14612 , H01L27/14603 , H04N5/351 , H04N5/3658 , H04N5/369 , H04N5/374 , H04N5/378
Abstract: A semiconductor device includes a pixel array, a plurality of column circuits, an amplifier, switch arrays of a first layer to an nth layer, and signal lines of the first layer to the nth layer. n is an integer of two or more. The switch array of an ith layer is disposed between the switch array of an (i+1)th layer and the amplifier. i is an integer of one or more and less than n. The signal line of the first layer is connected to the nth amplifier. The signal line of the nth layer is connected to the switch array of the nth layer. Each of the plurality of switches included in the switch array of the nth layer is connected to the column circuit.
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公开(公告)号：US20170041558A1
公开(公告)日：2017-02-09
申请号：US15297685
申请日：2016-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
IPC: H04N5/341 , H04N5/369 , H04N5/378 , H04N5/3745
CPC classification number: H04N5/341 , H04N5/3692 , H04N5/3698 , H04N5/37457 , H04N5/376 , H04N5/3765 , H04N5/378
Abstract: An image sensor includes n light receiving elements including first to n-th light receiving elements, each of the light receiving elements generating photoelectric conversion signals, n sequencers including first to n-th sequencers, each of the sequencers having both a sequencer input terminal to which a k-th horizontal control signal is input, and a sequencer output terminal from which a (k+1)-th horizontal control signal is output, and n switches including first to n-th switches, each of the switches having a switch input terminal to which a signal corresponding to the photoelectric conversion signal is input, a switch control terminal to which a k-th pixel control signal is input, and a switch output terminal which is electrically connected to the switch input terminal, wherein n is a natural number of 2 or more, and k is a natural number of 1 to n.
Abstract translation: 图像传感器包括n个光接收元件，包括第一至第n光接收元件，每个光接收元件产生光电转换信号，n个定序器包括第一至第n个定序器，每个定序器都具有定序器输入端 输入第k个水平控制信号的定序器输出端子，输出第（k + 1）个水平控制信号的定序器输出端子，并且n个开关包括第一至第n开关，每个开关具有开关 输入与光电转换信号相对应的信号的输入端子，输入第k个像素控制信号的开关控制端子和与开关输入端子电连接的开关输出端子，其中n为 2以上的自然数，k为1〜n的自然数。
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